Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Kabsuhiki Kaisha Toshiba

Fumitaka Arai

Riichiro Shirota

Yasuhiko Matsunaga

Tatsuya Kato

Atsuhiro Sato

Makoto Sakuma

Wataru Sakamoto

Satoshi Nagashima

Yuta Watanabe

Yoshio Ozawa

Tomoharu Tanaka

Takashi Mori

Ken Takeuchi

Makoto Mizukami

Masayuki Ichige

Susumu Fujimura

Katsuyuki Sekine

Toshitake Yaegashi

Kikuko Sugimae

Akihito Yamamoto

Akira Shimizu

Toshiyuki Iwamoto

Atsushi Murakoshi

Keisuke Kikutani

Ichiro Mizushima

Masahiro Kiyotoshi

Keiji Hosotani

Takeshi Kamigaichi

Nobutoshi Aoki

Masaki Kondo

Keisuke Nakatsuka

Kiyohito Nishihara

Hisataka Meguro

Hiroshi Watanabe

Takuya Futatsuyama

Tomomasa Ueda

Kazuhiro Shimizu

Keiji Ikeda

Tsutomu Tezuka

Nobuyoshi Saito

Chika Tanaka

Kentaro Miura

Toshiyuki Enda

Masataka Takebuchi

Hiroyoshi Tanimoto

Masayuki Tanaka

Seiichi Aritome

Yuji Takeuchi

Akira Umezawa

Ryota Suzuki

Hiroaki Tsunoda

Toshiaki Edahiro

Hiroyuki Nitta

Tatsuya Okamoto

Yoshihiko Saito

Shinji Satoh

Koji Sakui

Atsuhiro Kinoshita

Yasuhito Yoshimizu

Shosuke Fujii

Yasuhiro Shiino

Shinya Arai

Kiwamu Sakuma

Tadashi Iguchi

Tomoaki Sawabe

Takehiro Hasegawa

Hiroshi Itokawa

Hidenori Miyagawa

Masato Endo

Kazuhito Narita

Hiroki Tokuhira

Hirohisa Iizuka

Norihiro Fujita

Fumie Kikushima

Hideaki Aochi

Masaru Kito

Ryota Katsumata

Mitsuru Sato

Takashi Kobayashi

Kazuyuki Higashi

Hiroyuki Kutsukake

Jun Fujiki

Kiyotaka Miyano

Takashi Izumida

Tomoya Sanuki

Hideto Takekida

Takeshi Murata

Akio Kaneko

Toshifumi Hashimoto

Norihisa Arai

Kunifumi Suzuki

Kiyomi Naruke

Daisuke Hagishima

Mutsuo Morikado

Kazumichi Tsumura

Takamitsu Ishihara

Takashi Ishida

Shinichi Sotome

Kotaro Fujii

Yasuhiro Uchiyama

A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.

Semiconductor memory device

A semiconductor memory device includes memory block regions arranged in a first direction, a hook-up region arranged in the first direction with respect to memory block regions, and a wiring region extending in the first direction and arranged with memory block regions and the hook-up region in a second direction. Each of memory block regions includes memory strings extending in the first direction and arranged in the second direction and a first wiring extending in the second direction and connected to memory strings in common. The wiring region includes a second wiring extending in the first direction and connected to first wirings corresponding to memory block regions in common. The hook-up region includes a third wiring connected to the second wiring and a contact electrode extending in a third direction and connected to the third wiring.

A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

Semiconductor memory device having contact plugs extend in the stacking direction of the plurality of the first and second conductive layers

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Semiconductor memory and method of manufacturing the same

According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, and at least one memory structure. The first conductive layer includes a first portion, a second portion, and a third portion, a fourth portion, and a fifth portion. The first portion is provided between the second portion and the third portion in a second direction. The second conductive layer includes a sixth portion, a seventh portion, and an eighth portion, a ninth portion, and a tenth portion. The sixth portion is provided between the seventh portion and the eighth portion in the second direction. The second portion is provided between the sixth portion and the eighth portion in the second direction.

According to one embodiment, a memory device includes: first and second stacks each including a first semiconductor layers arranged in a first direction perpendicular to a surface of a substrate, the first and second stacks arranged in a second direction parallel to the surface of the substrate; a second semiconductor layer above the first stack in the first direction; a third semiconductor layer above the second stack in the first direction; memory cells between the first semiconductor layers and the word lines; a first transistor on the second semiconductor layer; and a second transistor on the third semiconductor layer. The first and second stacks are arranged at a first pitch, the first and second semiconductor layers are arranged at a second pitch equal to the first pitch.

Memory device and method of controlling memory device

A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

Semiconductor memory device incorporating hafnium oxide insulative portions

According to one embodiment, a semiconductor memory device includes first and second semiconductor layers and a first conductive layer. The first and second semiconductor layers extend in a first direction. The second semiconductor layer is stacked above the first semiconductor layer in a second direction intersecting the first direction. The first conductive layer intersects the first and second semiconductor layers and extends in the second direction. The first conductive layer includes first and second portions intersecting the first and second semiconductor layers respectively. A width of the first portion in the first direction is smaller than a width of the second portion in the first direction. A thickness of the first semiconductor layer in the second direction is larger than a thickness of the second semiconductor layer in the second direction.

A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.

Semiconductor memory device and method for manufacturing same

According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.

Semiconductor memory device having a memory cell and semiconductor layer

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

Stacked type semiconductor memory device and method for manufacturing the same

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Yokohama, Japan

Fumitaka Arai