Hitachi, Ltd.

Fumio Yuuki

Hiroki Yamashita

Masayoshi Yagyu

Tatsuya Kawashimo

Takeshi Kato

Keiichi Yamamoto

Katsuya Tanaka

Koji Fukuda

Masahito Sonehara

Hisaaki Kanai

Ryo Nemoto

Teruhisa Shimizu

For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an 'H' level and a latch part that latches a data output signal from the data acquisition part when the click signal is an 'L' level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an &#x201c;L&#x201d; level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

Logic circuit

A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.

Level conversion circuit

A first current source generating a current I+I when a control signal is in 'H' level and a current Iwhen it is in 'L' level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I+I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in &#x2018;H&#x2019; level and it is in an inactive state when the signal is in &#x2018;L&#x2019; level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.

A clock data recovery circuit has a good jitter tolerance characteristic and a broad data recovery range in the event of a wander, that is, a good wander-tracking characteristic of a recovered clock signal. The clock data recovery circuit executes control to compare the position of the edge of data with the position of the edge of a data recovery clock signal (a recovered clock signal) and keeps the clock edge away from the data edge if a gap between the edges becomes smaller than a reference value. A cycle of a reference clock signal is divided into N portions to generate N clock signals (pl ) with phases different from each other in composition circuits. By executing control to turn on 2 of the N selector control signals supplied to each 2 adjacent pins of the N&#x2212;1 selectors at the same time, the N&#x2212;1 selectors are capable of generating a middle phase between first and second phases and, hence, generating one of N&#xd7;2 phases from N input phases as the phase of the data recovery clock signal.

Clock and data recovery method and digital circuit for the same

A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zand a magnetic head, the transmission lines are formed so that the characteristic impedances Z, Z, and Z(n&#x2267;2) thereof on the output driver side are higher than those on the magnetic recording head side (Z&#x3e;Z&#x3e;Z), and the impedance Zof the output driver is equal to or higher than the characteristic impedance Zof the transmission line.

Magnetic recording device

This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.

Signal transmission circuit, signal output circuit and termination method of signal transmission circuit

A processor or a semiconductor integrated circuit has circuit blocks performing signal processing, internal power supply nets, noise detecting circuits corresponding to each circuit block that detect noise on the power supply nets and an interruption handling circuit that prevents a malfunction in processing within a circuit block caused by noise on the power supply nets. When noise is detected, the interruption handling circuit performs an interruption by sending an interruption signal to the circuit block relating to the signal processing for preventing a malfunction to the circuit block. During the operation of a plurality of stages for executing an instruction, noise is monitored at every stage. If no noise is detected through a final stage, the result is outputted. If noise is detected at any one of the stages, then an interruption process is performed.

Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets

The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.

Growing community of inventors

Fujimino, Japan

Fumio Yuuki