Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Nippon Telegraph and Telephone Public Corporation

Fumio Sugiyama

Shigeru Asakawa

Makoto Nakamura

Toshiaki Watanabe

Kenshi Dachiku

Shigenori Okamoto

Tsukasa Okai

Mitsushi Ikeda

Kouhei Suzuki

Hisao Fujiwara

Akio Gotoh

Isao Tashiro

Kazuo Ozeki

Akio Goto

The present invention provides a liquid crystal display device, having light-converging member provided for each pixel or each pixel row consisting of a plurality of pixels for converging the light incident from the outside, first light path converting member for converting the converged light into a parallel light, light separating member for separating the parallel light into its red-, green- and blue-light components, a liquid crystal cell for controlling the transmitting amount of each light component, and control member for controlling the light transmittance of the liquid crystal cell for a plurality of pixels by applying a voltage to the liquid crystal cell.

Reflection type liquid crystal display device capable of color display

An image coding apparatus includes an image dividing circuit for dividing an image signal of one frame into a plurality of blocks, an amount-of-data calculator for computing the amount of data representing fineness of a picture included each block, a bit-assignment determining circuit for distributing all coding bits usable for encoding the image signal of one frame to the individual blocks, to each block a number of bits which has been determined by the amount of data of the block, a quantizer for quantizing the image signal for each block and outputting a quantization signal, and an encoder for encoding the quantization signal in accordance with the number of bits of each block determined by the bit-assignment determining circuit.

Image compression coding system

An input image signal is divided into blocks each of 8 x 8 pixels, is subjected to cosine transform and is then converted to a signal of a spatial frequency region. After the cosine transform, the data is subjected to subtraction with respect to first to fourth types of data. Data of the same block of the one previous frame is used as the first data to provide a first difference between frames. Data of different blocks in the same frame is used as the second data to provide a second difference within the same frame. The third data is background image data and the fourth data is specific data. The minimum one of the first to fourth difference data is selected, and is then quantized and transmitted. Accordingly, a difference data involving a small amount of information to be transmitted can be selected for each block, thus always realizing a high transmission efficiency irrespective of the degree of image change.

Image transmission apparatus

In an image transmitting system such that an image frame is divided into plural blocks and video signals are transformed block by block in accordance with an orthogonal transform method before coding and transmission of the transform coefficients, transform coefficients are coded, only when differences in transform coefficient between the preceding frame and the current frame are significant, to reduce the coding speed and therefore the video signal transmission speed. In addition, transform coefficients are weighted under consideration of human visual characteristics (the weighting is increased with decreasing order of transform coefficient). Further, when only differences in transform coefficient are coded and transmitted, it is possible to further reduce the transmission speed.

Divisional image transmission system and method

An improved linear prediction filter based on the PARCOR lattice structure of Itakuro and Saito, replaces the correlator by a recursive loop including a coefficient generator, coefficient corrector, and attenuator, such that the corresponding filter output is suppressed to a minimum value.

Adaptive linear prediction filters

A security communication system comprises a transmission apparatus including a scrambling circuit for scrambling an information signal according to a specific code and a reception apparatus including a deciphering circuit for deciphering an output signal of the transmission apparatus according to substantially the same code as the specific code. The transmission apparatus further includes a first signal generating circuit for supplying a synchronizing signal to the scrambling circuit to drive the same, a signal synthesizing circuit having a first input terminal coupled to the output terminal of the first signal generating circuit, and a switching circuit connected between the output terminal of the scrambling circuit and a second input terminal of the signal synthesizing circuit, said switching circuit being opened while the first signal generating circuit is generating a synchronizing signal. The reception apparatus further includes a second signal generating circuit and a synchronization circuit for supplying a drive signal to the deciphering circuit when the synchronizing signal component in the output signal of the transmission apparatus synchronizes with the output signal of the second signal generating circuit.

Security communication system

Disclosed is an arithmetic operation apparatus for an electrical watt-hour meter for cumulatively adding products arrived at by multiplying two input signals in succession which correspond respectively to a line voltage and line current. The apparatus comprises a pulse width modulator for modulating a first input signal of line voltage into the form of a pulse width for each sampling period. A certain number of the sampling periods is taken as a first arithmetic operation period (hereinafter referred to as 'a first unit operation period'). During the first unit operation period, a second input signal of line current is supplied for a length of time corresponding to each modulated pulse width of the first input signal. The second input signals thus supplied are integrated by a first integrator during each first unit operation period. During a succeeding operation period consisting of the same specified number of sampling periods (hereinafter referred to as 'a second unit operation period'), a reference signal which has a polarity opposite to that of the integrated signal at the end of the first unit operation is reversely integrated by the first integrator. During the second unit operation period in which the above-mentioned reverse integration is carried out, the second input signal which is to be integrated for a length of time corresponding to the modulated pulse width of the first input signal is conducted to a second integrator to be integrated during the respective sampling periods. Each of the first and second integrators alternately carries out the integration and the reverse integration during the alternately recurring first and second unit operation periods following the aforesaid ones. A counter counts a number of clock pulses issued for a length of time varying with the reverse integration applied each time. The number of clock pulses thus counted are added in succession, thereby determining a cumulatively added sum of the multiplication products of the first and second input signals which corresponds to a watt-hour value.

Arithmetic operation apparatus for an electronic watt-hour meter

In a security communication system, the transmitting unit includes a sample - hold circuit for sampling and holding the original voice signal, an inverting circuit for inverting the polarity of the samples of the voice signal in accordance with a first code, an adder circuit for adding a D.C. signal to the output signal of the inverting circuit, and another inverting circuit for inverting the polarity of the samples of the output signal of the adder circuit in accordance with a second code. The receiving unit includes a sample - hold circuit for sampling and holding the received signal, a synchronizing circuit for extracting a synchronizing signal component from a received signal during, for example a period of non-voice transmission, and for synchronizing the transmitting unit with the receiving unit, an inverting circuit for inverting the polarity of the samples of the received signal in accordance with the second code, a circuit for removing a D.C. signal component from the output of the inverting circuit, and a polarity inverting circuit for restoring the received signal from which the D.C. signal has been removed by said removing circuit to the original voice signal through the polarity inversion of the received signal in accordance with a third code.

Security communication system using polarity inversion

Receiving conditions are classified into three types-- 'good condition', 'intermediate condition' and 'bad condition'. Where the receiving condition is an 'intermediate condition,' a receiving section continues with a receiving operation by supplying power thereto through a first normally closed switch from a power source. Where the receiving condition is both a 'good condition' and a 'bad condition', the first normally closed switch is closed, only during a specific period having the necessary information signals supplied from a time band designating means, to supply power from the power source to the receiving section thus to extract the necessary information signals by a signal processing section from the receiving input signals supplied from the receiving section, whereas the first normally closed switch is opened, during the remaining period to interrupt the power supply from the power source to the receiving section thus to stop the receiving operation.

Time division multiplex communication receiving apparatus

A bit synchronization circuit which comprises a pulse generator for producing a pulse corresponding to a data signal received; a clock pulse oscillator for supplying a clock pulse having a frequency as high as four times the data speed of said data signal; a synchronization-controlling circuit supplied with signals from said pulse generator and clock pulse oscillator to produce a signal with a prescribed phase relative to a pulse delivered from said pulse generator; a ring counter whose reset terminal is supplied with an output signal from said synchronization-controlling circuit and whose count terminal is impressed with a clock pulse produced from said clock pulse oscillator; and a flip-flop circuit whose set terminal is supplied with the content '0' of said ring counter and whose reset terminal receives the content '2' thereof, thereby generating an output pulse synchronous with said data signal received.

Growing community of inventors

Sagamihara, Japan

Fumio Sugiyama