Matsushita Electric Industrial Co., Ltd.

Renesas Technology Corp.

Fumio Iwamoto

Susumu Matsumoto

Michinari Yamanaka

Junjiro Sakai

Yasutaka Nishioka

Shingo Tomohisa

It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole () reaching an etching stopper film () is formed, annealing is carried out at 300 to 400&#xb0; C. with the via hole () opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring () which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film () and an interlayer dielectric film () having a low dielectric constant and a by-product staying in an interface of the etching stopper film () and the interlayer dielectric film () having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

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Kyoto, Japan

Fumio Iwamoto