Fujitsu Corporation

Fujitsu Vlsi Limited

Fumio Baba

Hirohiko Mochizuki

Yoshihiro Takemae

Masao Nakano

Hatsuo Miyahara

Tomio Nakano

Kiyoshi Miyasaka

Jun-ichi Mogi

Junichi Kasai

Atsushi Hatakeyama

Mitsutaka Sato

Seiji Enomoto

Kazuya Kobayashi

Tsutomu Mezawa

Takashi Yabu

Hiroaki Ogawa

Hiroshi Nagayama

A semiconductor device includes a first chip having a circuit arrangement, and a plurality of first terminals formed on a main surface of the first chip and substantially arranged into a line. The semiconductor device also includes a second chip having a circuit arrangement identical to that of the first chip, and a plurality of second terminals formed on a main surface of the second chip and substantially arranged into a line. The first and second chips are arranged in a predetermined direction perpendicular to the main surfaces of the first and second chips. The semiconductor device also includes a plurality of connecting members connected to the first terminals and the second terminals and provided for external connections.

Semiconductor device having a plurality of chips having identical

A semiconductor memory device storing data having a unit of N bits (N is an integer) includes M memory elements (M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data, and M internal bus lines each carrying one-bit data and connected to a corresponding one of the M memory elements. A designating circuit receives an address signal from an external device and designates one of the plurality of blocks of each of the M memory elements so that M blocks are designated by the address signal. A ROM stores information on whether or not each of the plurality of blocks of each of the M memory elements has a defective memory cell and outputs the information in accordance with the address signal. N external bus lines individually carry one-bit data. A bus line switching circuit determines whether each of the M blocks designated by the designating circuit has a defective memory cell by referring to the information from the ROM, and selectively connects N internal bus lines among the M internal bus lines to the N external bus lines so that one of the M blocks which has a defective memory cell is prevented from being selected and another one of the M blocks is selected.

Semiconductor memory device having information indicative of presence of

A semiconductor memory device having a register and a memory cell array includes a controlling circuit for disconnecting an input/output circuit from a data bus and turning OFF a transfer gate provided between the register and data bus in a first operation mode and for connecting the input/output circuit to the data bus and turning ON the transfer gate in a second operation mode. In the first operation mode, a data read or write operation is performed between the memory cell array and an external circuit, and alternatively in the second operation mode the data read or write operation is performed between the register and the external circuit.

Semiconductor memory device having a register

A dual-port semiconductor memory device having one serial memory cell of a serial access memory provided for a predetermined number of bit line pairs. A transfer gate circuit is provided between the serial memory cell and the predetermined number of bit line pairs so that only one bit line pair is selectively coupled to one serial memory at one time. Access to the dual-port semiconductor memory device is made in n/m stages when there are n bit line pairs and m serial memory cells in the serial access memory.

Dual-port semiconductor memory device

A semiconductor memory device having a data inverting circuit for selectively inverting an input/outpt data of a sense amplifier in such a way that the charging states of respective memory cells connected to two bit lines in each bit line pair become equal for the same input/output data. A clamp circuit draws the potentials of all of the bit lines to a predetermined potential in response to a clear control signal, whereby the contents of all of the memory cells are cleared at the same time.

Semiconductor memory device

A semiconductor device having a dynamic circuit and a static circuit, wherein a clock signal, in synchronization with the operation of the static circuit, initiates the operation of the dynamic circuit. A delay circuit of a static type is provided to delay the clock signal and generate a delayed clock signal. The delayed clock signal initiates operation of one stage of the dynamic circuit. As a result, the final-operation timing of the dynamic circuit is substantially controlled by the delayed clock signal, thereby matching the operation of the dynamic circuit with the operation of the static circuit, regardless of the power supply voltage.

Semiconductor device having matched-timing dynamic circuit and static

A semiconductor memory device operated synchronously with clock signals, such as a MOS dynamic RAM device. The semiconductor memory device includes a switch circuit inserted between a prestage output amplifier circuit receiving a readout signal from a memory cell and an output buffer circuit. The switch circuit is turned on just before the output signal is supplied from the prestage output amplifier circuit to the output buffer circuit and turned off after the output condition of the output buffer circuit is settled. The potential corresponding to the output data is maintained in the circuit between the switch circuit and the output buffer circuit. The output condition of the output buffer circuit is therefore retained even during the reset period of the prestage drive circuit, and the duration period of the output signal is expanded.

In a semiconductor memory device, memory cells (1-1 to 1-4, 1'-1, 1'-2) are divided into a plurality of blocks (BK.sub.1, BK.sub.2) in which a plurality of pairs of sense lines (S.sub.1, S.sub.1, . . . , S.sub.4, S.sub.4) are provided. The sense lines are commonly connected to each other, i.e., the sense lines of one block (BK.sub.1) are connected to the respective sense lines of the other block (BK.sub.2). The sense relationship between two adjacent sense lines (S.sub.1, S.sub.2) belonging to one block (BK.sub.1) is opposite to the sense relationship between the corresponding two adjacent sense lines (S.sub.1, S.sub.2) belonging to the other block (BK.sub.2).

Block-divided semiconductor memory device

A dual port type semiconductor memory using a dynamic type random access memory (RAM) includes; a plurality of word lines, a plurality of pairs of bit lines, and a dynamic type RAM connected at each intersection of the word lines and the bit lines. The semiconductor memory further includes a first column decoder connected to a writing-reading out bus through a pair of gates (G.sub.1) including two transistors directly connected to each of the bit lines, and a second column decoder connected to a reading out bus through a pair of gates (G.sub.2) including four transistors. Gates of two of the four transistors of the second pair of gates are connected to each bit line. The other two of the four transistors are connected to the reading out bus.

Dual port type semiconductor memory

A clock generating circuit includes a switch control circuit controlling a C-MOS circuit including first and second transistors having first and second conductivity types, respectively. Also included in the clock generating circuit is a bootstrap capacitor having a first end connected to the junction between the first and second transistors. The switch circuit includes a third transistor, having the first conductivity type, connected between the gate of the first transistor and the junction between the first and second transistors, and a fourth transistor, having the second conductivity type, connected between the gates of the first and second transistors. The gate of the second transistor is connected to receive an input clock signal and the gates of the third and fourth transistors are connected together to receive a delayed clock signal produced by delaying the input clock signal. The second end of the bootstrap capacitor is connected to receive a further delayed and inverted clock signal. When the delayed clock signal has a first value, the switching circuit connects the gates of the first and second transistors together and an output signal with a first level is produced at the junction of the first and second transistors. When the delayed clock signal reaches a second level, the switching circuit connnects the gate of the first transistor to the junction of the first and second transistors and the bootstrap capacitor boosts the output signal to a second level.

Clock generating circuit providing a boosted clock signal

A semiconductor memory device having matrix-arranged memory cells, carrying out data write or read operations to or from a selected memory cell through a pair of data buses by the selection of a word line and a pair of bit lines, includes two transfer devices which transfer data between bit lines and data buses and which are separately operated for either writing or reading. Even if a data read operation is stopped midway by a system reset or the like, the stored data in the memory cell is not destroyed.

A buffer circuit has first and second boot-strap circuits. The first boot-strap circuit charges the gate of an output MOS transistor to a voltage above a supply voltage when an input signal has a first logic level. The gate of a precharging MOS transistor in the first boot-strap circuit is driven by the second boot-strap circuit so as to precharge a capacitor in the first boot-strap circuit to a voltage above the supply voltage when the input signal has a second logic level.

Double bootstrapped clock buffer circuit

An integrated semiconductor circuit device is provided with a special purpose readable indicator without providing additional pins. The indicator may be utilized to store information pertinent to the operativeness of the integrated circuit. The results of quality control monitoring may be written into the store to serve as a flag. A specific application is in semiconductor memory arrays having redundancy memory capability to automatically replace defective memory cells in the primary array. To enable one to know whether or not the redundancy memory array is being used, this information is written into a quality control storage cell. This cell may be a ROM system which may be accessed during a check mode.

IC with built-in electrical quality control flag

A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.

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Kawasaki, Japan

Fumio Baba