Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Fumio Arakawa

Tetsuya Yamada

Kunio Uchiyama

Susumu Narita

Masayuki Ito

Norio Nakagawa

Yonetaro Totsuka

Osamu Nishii

Junichi Nishimoto

Tetsuhiko Okada

Makoto Ishikawa

Motonobu Tonomura

Makoto Toda

Takehiro Shimizu

Hiroshi Tanaka

Koichiro Ishibashi

Hiroyuki Mizuno

Takao Watanabe

Takayuki Kawahara

Nobuyasu Kanekawa

Masatoshi Hoshino

Kohei Sakurai

Ikuya Kawasaki

Naoki Kato

Naohiko Irie

Hirokazu Aoki

Kentaro Yoshimura

Masaaki Shimizu

Ken Naono

Takanobu Tsunoda

Yohei Akita

Tetsuro Honmura

Mark Hill

The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.

Data processor selecting a flag out of a plurality of flags generated by an instruction operating on multiple operand sizes in parallel

In the data processor in which a combination of multiple specific instructions is prohibited, an instruction set is employed that additionally defines that prohibition combination pattern as a separate instruction. With respect to the prohibition combination pattern additionally defined as the separate instruction, for example, in order to make a definition in such a manner that an instruction dispatch mechanism for the instruction set that is present before the additional definition is used as is, the instruction to be additionally defined by the prohibition combination pattern is limited to an instruction type that is the same as the instruction defined only with a latter-half code of the instruction in a case of an instruction set in which the instruction set that is present before the additional definition includes a prefix code.

Data processor with extended instruction code space including a prohibition combination pattern as a separate instruction

Instructions for generating flags according to operands' data sizes, and instruction sets handled by a RISC data processor including an instruction capable of executing an operation on operands in more than one data size are disclosed. An identical operation process is conducted on the small-size operand and on low-order bits of the large-size operand, and flags are generated capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation. Thus, a reduction in instruction code space of the RISC data processor can be achieved.

Data processor including prefix instruction selecting a flag out of a plurality of flags generated by a subsequent instruction operating on multiple operand sizes in parallel

For efficient issue of a superscalar instruction a circuit is employed which retrieves an instruction of each instruction code type other than a prefix based on a determination result of decoders for determining instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant. When an instruction of a target code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target code type as prefix code candidates. When an instruction of a target code type cannot be detected at the rear end of the instruction units, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head.

Executing prefix code to substitute fixed operand in subsequent fixed register instruction

A RISC data processor in which the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. An instruction for generating flags according to operands' data sizes is defined, and an instruction set handled by the RISC data processor includes an instruction capable of executing an operation on operands in more than one data size. An identical operation process is conducted on the small-size operand and on low-order bits of the large-size operand, and flags are generated capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation. Thus, a reduction in instruction code space of the RISC data processor can be achieved.

RISC processor with instruction executing on different size operand and prefix instruction identifying select flag update for respective size

Flag generation and use in processor with same processing for operation on small size operand as low order bits portion of operation on large size operand

The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an instruction of each instruction code type other than a prefix on the basis of a determination result of decoders for determining an instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant to instruction executing means. When an instruction of a target instruction code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target instruction code type as prefix code candidates. When an instruction of a target instruction code type cannot be detected at the rear end of the instruction units to be searched, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target instruction code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head.

Processing prefix code in instruction queue storing fetched sets of plural instructions in superscalar processor

A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.

Vector SIMD processor

A vehicular control system which includes a user parameter input module, an external parameter input module, a plurality of objective functions, a policy setting module, and a policy node. The user parameter input module Inputs a user parameter. The external parameter input module inputs an external parameter resulting from an outside environment. The objective functions are set for each control characteristic, respectively, so as to calculate an internal parameter of each control target from the user parameter and the external parameter. The policy setting module sets policies indicating a control index of the user for the objective functions respectively. The policy node weights the objective functions on the basis of the policies, adjusts the internal parameter in accordance with the policy so that the internal parameter is optimized among the objective functions, and issues a command to a control node corresponding to the internal parameter.

Vehicular control system and control method

The data processor executes an instruction having a direction for write to a reference register of other instruction flow and an instruction having a direction for reference register invalidation. The data processor is arranged as a data processor having typical functions as an integrated whole of processors (CPUand CPU) which execute simple instruction flows. When executing the instruction having a direction for write to a reference register of other instruction flow, the processor confirms whether a write register is invalid. The processor waits for the register to be made invalid, if the register is not invalid, and performs write if the register is invalid. After having executed the instruction having a direction for reference register invalidation, the processor invalidates the register to which a reference has been made. When the reference register is invalid, execution of the referring instruction is suspended until it is made valid.

Data processor

A first object of the present invention is to reduce interrupt to a CPU which occurs when microprocessors that are connected by a network receive a packet from the network to efficiently operate the processors. A second object of the present invention is to provide a microprocessor and a communication method, which make it possible to reply a quick response to the microprocessor at the transmitting side. Each of the microprocessors includes the CPU and a communication module. The communication module includes a register that stores information which is managed by the microprocessor. The communication module compares information at a given bit position within the packet which is inputted through the network with information retained in the register, and determines whether a process corresponding to the packet reception is conducted by the CPU, or not, according to the comparison result.

Microprocessor, network system and communication method

A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFFbetween the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

Semiconductor integrated circuit including multiple basic cells formed in arrays

Growing community of inventors

Kodaira, Japan

Fumio Arakawa