Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Fuminari Tanaka

Satoshi Nonaka

Yasoji Suzuki

Hiroshi Shigehara

Masanori Kinugasa

Tetsuya Iida

Shigeru Atsumi

Kenji Matsuo

Yukihiro Saeki

Yoshihiro Iwamoto

Masayuki Sahoda

Munenobu Kida

Yasuo Kawahara

Yasushi Sato

Toru Yoshida

Hirokata Ohta

An output circuit of a semiconductor integrated circuit includes a plurality of output transistors having different current driving abilities for a load, and a plurality of signal delay means for delaying signals for driving each of the output transistors by different delay times, wherein the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a first delay time is set to be larger than the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a second delay time shorter than the first delay time.

Output circuit of semiconductor integrated circuit with reduced power

In an output circuit for use in a semiconductor IC comprising a CMOS transistors constituting an output buffer, a transfer gate of CMOS structure is connected between the gates of the CMOS transistors as a resistive element. The transfer gate reduces the changes in the gate potentials of output transistors, which occur when logic inputs are supplied to the gates of the output control transistors. Hence, the deformation of the output waveform, which has resulted from the through currents flowing through the output transistors, is minimized.

Output control circuit for reducing through current in CMOS output buffer

A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.

Input protecting circuit in use with a MOS semiconductor device

An output circuit includes a plurality of output buffer circuits and a plurality of pre-buffer circuits connected to drive the output buffer circuits. Some of the pre-buffer circuits are each constituted by P- and N-channel MOS transistors having channel widths or channel lengths which are large enough to drive the output buffer circuits, and the remaining pre-buffer circuits are each constituted by P- and N-channel MOS transistors whose channel widths and channel lengths are so determined as to set the current driving ability thereof sufficiently smaller than that of the corresponding output buffer circuits.

Output circuit for CMOS integrated circuit with pre-buffer to reduce

Extension directions of source electrode layer and a drain electrode are parallel to rows or columns of an array of alternately arranged source regions and drain regions, thereby forming widths of source and drain electrode layers wider than those of a conventional transistor to obtain a large mutual conductance.

Insulated gate type field effect transistor

In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage.

Highspeed parallel adder with clocked switching circuits

A speech synthesizing apparatus has a first memory storing a plurality of phrase data each including speech data, an address designating circuit for designating an address of the first memory, a second memory for storing synthesizing condition data, and a synthesizer for synthesizing a speech signal based on speech data from the first memory in accordance with the synthesizing condition data stored in the second memory. Each phrase data stored in the first memory also includes the corresponding synthesizing condition data. When each phrase data is read out from the first memory, the synthesizing condition data is first read out and is stored in the second memory, and then the speech data is read out and is supplied to the synthesizer.

Speech synthesizing apparatus

A C-R type D/A converter which comprises a C-array type D/A converter used to convert the upper bit data of a digital input data on a digital-to-analog basis, an R type D/A converter used to convert the lower bit data of the digital input data, and a coupling capacitor connected between an output terminal of the C-array type D/A converter and an output terminal of the R type D/A converter.

C-R type D/A converter

An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances C.sub.mP12, C.sub.mP13, C.sub.mN12, C.sub.mN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance C.sub.mN11 of the first n channel MOS transistor and the mirror capacitance C.sub.mP11 of the first p channel MOS transistor.

Analog switch circuit having output offset compensation circuit

A dynamic read only memory comprises a plurality of ROM blocks and a control circuit composed of a plurality of MOSFETs respectively connected to the column lines. The control circuit keeps the data from the ROM block not containing a specified memory cell at a discharged level.

Dynamic read only memory

An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.

Integrated circuit

There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.

Growing community of inventors

Kawasaki, Japan

Fuminari Tanaka