Mitsubishi Electric Corporation

Fumihito Masuoka

Katsumi Nakamura

Ze Chen

Yuki Haraguchi

Akito Nishii

Takao Kachi

Koji Tanaka

Akihiko Furukawa

Hidenori Fujii

Tsuyoshi Kawakami

Shigeto Honda

Yasuhiro Yoshiura

Yuji Murakami

An object of a technique of the present disclosure is to suppress reduction in withstand voltage in a power semiconductor device. A semiconductor base includes an n&#x2212; type semiconductor substrate and at least one p type diffusion layer formed separately from each other on a surface layer on a side of a first main surface of the semiconductor substrate in a terminal region. A power semiconductor device includes at least one insulating film formed on a first main surface of the semiconductor base between an insulating film and the insulating film. A semi-insulating film has contact with the insulating film on the insulating film, and has contact with the first main surface in at least two regions where the insulating film is not formed between the insulating films.

Power semiconductor device

The semiconductor device includes: a fourth impurity layer disposed in a state of being connected to the outermost peripheral second impurity layer and being separated from the first impurity layer between the outermost peripheral second impurity layer and the first impurity layer of the terminal portion, the fourth impurity layer having a second conductivity type and having an impurity concentration lower than an impurity concentration of the second impurity layer; an insulating film disposed on at least a part of the terminal portion, the insulating film having a first opening on the first impurity layer; and an electrode disposed on the insulating film, the electrode connected to the first impurity layer via the first opening.

Semiconductor device

A semiconductor device, which is a diode, includes the following: an n cathode layer, which is an n-type region, disposed in a surface layer of a semiconductor substrate; a p cathode layer, which is a p-type region, disposed in the surface layer; and a cathode electrode, which is a metal electrode, in contact with both of the n cathode layer and the p cathode layer. The cathode electrode includes a first metal layer in contact with both of the n cathode layer and the p cathode layer, and a second metal layer disposed on the first metal layer. A contact surface between the first metal layer and the second metal layer has an oxygen concentration lower than the oxygen concentration of a contact surface between the first metal layer, and the n cathode layer and the p cathode layer.

The semiconductor device according to the present invention includes: an n-type semiconductor substrate; a p-type anode layer provided in a front surface of the n-type semiconductor substrate; an anode electrode provided on the p-type anode layer; and a wire connected to the anode electrode, the p-type anode layer includes: a p-type anode layer disposed to include a position right under a portion where the wire is connected; and a p-type anode layer disposed to exclude the position right under the portion where the wire is connected, and an impurity concentration of the p-type anode layer is higher than an impurity concentration of the p-type anode layer.

Semiconductor device and manufacturing method thereof

A p type anode layer is formed on a front surface of an n type drift layer in an active region. An n type buffer layer is formed on a rear surface of the ntype drift layer. An n type cathode layer and a p type cathode layer are formed side by side on a rear surface of the n type buffer layer. An n type layer is formed on the rear surface of the n type buffer layer in a boundary region between the active region and the terminal region side by side with the n type cathode layer and the p type cathode layer. An extending distance of the n type layer to the active region side with an end portion of the active region as a starting point is represented by WGR1, and WGR1 satisfies 10 &#x3bc;m&#x2264;WGR1&#x2264;500 &#x3bc;m.

Semiconductor device with backside N-type layer at active region/termination region boundary and extending into action region

First and second p-type anode layers () are provided side by side on a drift layer (). N-type cathode layer () and p-type cathode layer () are provided side by side below the drift layer (). An n-type buffer layer () is provided between the drift layer () and the n-type cathode layer () and between the drift layer () and the p-type cathode layer (). The first p-type anode layer () has a greater diffusion depth than a diffusion depth of the second p-type anode layer (). The first p-type anode layer () has a greater impurity concentration than an impurity concentration of the second p-type anode layer (). The n-type cathode layer () has a greater diffusion depth than a diffusion depth of the p-type cathode layer (). The n-type cathode layer () has a greater impurity concentration than an impurity concentration of the p-type cathode layer ().

A p-type anode layer () is provided on an upper surface of an n-type drift layer (). An n-type cathode layer () is provided on a lower surface of the n-type drift layer (). An n-type buffer layer () is provided between the n-type drift layer () and the n-type cathode layer (). A peak impurity concentration in the n-type buffer layer () is higher than that in the n-type drift layer () and lower than that in the n-type cathode layer (). A gradient of carrier concentration at a connection between the n-type drift layer () and the n-type buffer layer () is 20 to 2000 cm.

An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate.

Semiconductor device including an electric field buffer layer and method for manufacturing same

An insulating film () is formed on a main surface of a semiconductor substrate () that includes an active region and a termination region. The insulating film () in the active region is etched to form an opening (). The insulating film () is used as a mask and an impurity is implanted into the semiconductor substrate () in a direction tilted by 20&#xb0; or more from a direction normal to the main surface of the semiconductor substrate () while rotating the semiconductor substrate () to form a diffusion layer () in the active region. The diffusion layer () extends wider than the opening () up to below the insulating film () on the termination region side.

Method for manufacturing semiconductor device

A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer.

Growing community of inventors

Tokyo, Japan

Fumihito Masuoka