Kabushiki Kaisha Toshiba

Other

Fujitsu Corporation

Fumihiro Kohno

Hironobu Akita

Shinichiro Shiratake

Kenji Tsuchida

Toshimi Ikeda

Haruki Toda

Tsuneo Inaba

A semiconductor memory having memory cells each storing first data and second data in a memory cell array arranged in a column direction; a plurality of word lines connected to the memory cells in a row direction; and first and second bit lines, to which the first and second data are respectively read out, in the column direction. When one of the first and second bit lines changes from a first potential to a second potential lower than the first potential after data read out, the potential of the other bit line is changed from the second to the first potential, and if the electric potential of the selected bit line changes from the first to the second potential when data is read out, the other bit line is selected when the data is next read out, and, if the electric potential of the selected bit line maintains the first potential, the selected bit line is maintained selected even when the data is to be read out next.

Semiconductor memory and data read method of the same

A data memory circuit having divided several cache lines storing data, and several entries, and a tag circuit, are provided. The tag circuit having an array of an associative memory including a memory cell circuit having several memory cells storing address corresponding to the data stored in the data memory circuit and divided several rows, and a comparator circuit comparing the address stored in the memory cell circuit with input address, the comparator circuit comparing the address stored in divided several rows of the memory cell circuit with the input address concurrently in each of divided rows storing the address, and generating a cache hit/miss determination signal based on the comparative result of each row, the hit/miss determination signal being supplied to the data memory circuit.

Semiconductor memory device used for cache memory

A semiconductor memory device includes a memory cell array having a plurality of memory cells. The memory cells are arranged at intersections between a plurality of word lines and a plurality of bit lines. The semiconductor memory device also includes a row decoder section located adjacent to the memory cell array. The row decoder section has a plurality of decoder circuits which selectively drive the word lines. The semiconductor memory device further includes a control circuit section located adjacent to the row decoder section. The control circuit section has at least one control circuit whose part is arranged in the row decoder section.

Semiconductor memory device

One (first level shift circuit) of first and second level shift circuits is provided in a local word-drive-line driving circuit located near memory cell arrays. The second level shift circuit is provided in a global word-drive-line driving circuit located remote from the memory cell arrays.

Semiconductor memory device with reduced its chip area and power consumption

The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

Semiconductor device including a repetitive pattern

There are provided a plurality of CMOS configured pre-driver circuits, wherein an increased voltage obtained by increasing a power voltage is applied to a source of each P-channel transistor, and a word line driver circuit each having a P-channel transistor and an N-channel transistor to which an output of the pre-driver circuit is inputted. The source of each N-channel transistor in the plurality of pre-driver circuits is connected in common to that of each N-channel transistor in the word line driver circuit, and a source-drain path of an N-channel transistor for voltage alleviation is connected between this source common node and a node of a grounding voltage. The increased voltage is applied to a gate of the N-channel transistor for voltage alleviation.

Semiconductor integrated circuit for which high voltage countermeasure was taken

A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.

A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.

A memory cell array has a plurality of memory cells arranged in a matrix. A row decoder has a multiple selection period when a plurality of word lines are simultaneously selected and word lines are sequentially selected. A plurality of sense amplifiers are arranged for each bit line. These sense amplifiers are selectively connected to the bit lines by switch circuits formed on the bit lines. A sense amplifier receives data from memory cells on one bit line through a switch circuit. A plurality of word lines are simultaneously selected and sequentially set at a high level. Data from memory cells on one bit line are sequentially received by the sense amplifier and amplified.

Semiconductor memory device with high data read rate

Semiconductor memory device having level-shifted precharge signal

A semiconductor memory device adapted to enhanced functional features and a large memory capacity. The semiconductor memory device includes a semiconductor chip divided into 9 regions B1 through B9 having an identical area, in a 3.times.3 pattern. A main control block is arranged at least in a central region B9 and memory blocks are arranged respectively in the peripheral regions B1 through B8 of the 9 regions. Each of the memory blocks is controlled by the main control block and includes a data input/output circuit and a memory control circuit.

Growing community of inventors

Yokohama, Japan

Fumihiro Kohno