Other

Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Device Engineering Co., Ltd.

Fumihiko Arakawa

Takeshi Kusunoki

Hiroaki Nambu

Kazuo Kanetani

Kaname Yamasaki

Keiichi Higeta

Kunihiko Yamaguchi

Kenichi Ohhata

Nobuhiro Shiramizu

The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters. A clock signal synchronized with data at f/n Hz is converted by a multiplier so that the signal has a frequency of 'n' times so as to use the clock signal for triggering a flip-flop the operation frequency of which is fb/s in the synchronous digital circuit. The multiplier is arranged in the vicinity of the flip-flop triggered by the clock signal of fHz so as to avoid the effect of the deterioration of the operation frequency by interconnect capacitance. The maximum operation frequency of the transceiver circuit determined based upon the operating frequency of the synchronous digital circuit can be enhanced up to the maximum operation frequency of the flip-flop. As a margin can be produced in designing a frequency band of a clock signal processing circuit, the reduction of power consumption, the reduction of phase noise and the extension of a control frequency range can be realized.

Receiver circuit and transmitter circuit

To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit

In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Method of testing a semiconductor integrated device

Semiconductor integrated circuit

A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.

Signal transmission circuit and semiconductor memory using the same

To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic as configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.

Disclosed herein is a transmission circuit for transmitting a data signal between circuit units on a semiconductor integrated circuit through a signal wire. The data signal is transmitted by a driver circuit for precharging the signal wire to a high potential during a precharge period and discharging the signal wire to a low potential according to data to be transmitted during an evaluation period or keeping the signal wire at a high potential as floating as it is. Latch type Source-Coupled-Logic configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to a high potential during the precharge period, the second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire, is used as a receiving circuit, whereby a distinction as to a high or low level of the potential on the signal wire is made with early timing provided to perform the operation of discharging the signal wire by the driver circuit.

One of the factors determining cycle time of an SRAM is recovery time of a bit line after writing. When the size of a precharge PMOS transistor is increased to shorten the recovery time, delay time which is caused by making the precharge PMOS transistors non-conductive at the time of read operation, that is, access time increases. To avoid this, a semiconductor memory is provided with a second precharge circuit in addition to the conventional bit line precharge circuit. The second precharge circuit operates upon detection of completion of writing and stops operation when it detects that the bit line is precharged to a high potential. Consequently, the recovery time after write operation is shortened and the cycle time is reduced without increasing the access time.

Semiconductor memory

A semiconductor memory in accordance with the present invention includes a sense amplifier composed of a plurality of MOS transistors. When the sense amplifier is on standby, a first control circuit brings an input signal of the sense amplifier to zero. A second control circuit uses voltages developed because of an offset voltage occurring in the sense amplifier to feed back the potentials in the wells of the MOS transistors so that the offset voltage will be nullified. When the offset voltage occurring in the sense amplifier is nullified, a delay time required by the sense amplifier is shortened. This results in the high-speed semiconductor memory.

A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question. The bit line load circuit and the bit line recovery circuit include pMOS transistors whose drains are connected to the bit lines and whose gates are fed with a control signal, and diodes whose anodes are connected to a first power supply and whose cathodes are connected to sources of the pMOS transistors, the pMOS transistors and the diodes being furnished to each of the bit line pairs. The pMOS transistors are inhibited from conducting while the bit lines are being driven Low by the bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a read cycle. This constitution shortens the recovery time, implementing a high-speed SRAM with a shortened cycle time.

Growing community of inventors

Tokorozawa, Japan

Fumihiko Arakawa