Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Fumiaki Toyama

Yuki Mizutani

Masaaki Higashitani

Hiroyuki Ogawa

Shiqian Shao

Kwang-Ho Kim

Jee-Yeon Kim

Johann Alsmeier

Mohan Dunga

Chia-Lin Hsiung

Hirofumi Tokita

James K Kai

Peter Rabkin

Masatoshi Nishikawa

Akio Nishida

Jixin Yu

Takuya Ariki

Yan Li

Tuan Duc Pham

Seiji Shimabukuro

Takuya Futase

Chun Ge

Tomohiro Kubo

Ryoichi Honma

Alexander Chu

Hiroaki Koketsu

Yanli Zhang

Man Lung Mui

Tong Zhang

Seungpil Lee

Toru Miwa

Akira Inoue

Tai-Yuan Tseng

Murshed Chowdhury

Jin Liu

Masayuki Hiroi

Fumitaka Amano

Daxin Mao

Zhenyu Lu

Yoshitaka Otsu

Yuji Takahashi

Jongsun Sel

Kiyokazu Shishido

Kota Funayama

Takaaki Iwai

Noritaka Fukuo

Shigehiro Fujino

Kwang Ho Kim

Eiichi Fujikura

Yoko Furihata

Junji Oh

Sudarshan Narayanan

Kotaro Jinnouchi

Toshiya Yokota

Hiroto Ohori

Xin Yuan Li

Yuji Totoki

Qinghua Zhao

Guangyuan Li

Susumu Okazaki

Lishan Weng

Yanbin An

Akihiro Ueda

A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.

Non-volatile memory with inter-die connection

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a first three-dimensional memory array located in a first memory array region, and a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region. The alternating stack is laterally bounded by two trench fill structures that are laterally spaced apart along a second horizontal direction by an inter-trench spacing. The inter-array region includes a stepped cavity having vertical steps of the alternating stack that laterally extend along different horizontal directions. Multiple rows of contact via structures may contact different electrically conductive layers in the stepped cavity. Alternatively or additionally, a top portion of the stepped cavity and a width of a bridge region of the electrically conductive layers in the inter-array region may have a variable lateral extent along the second horizontal direction.

Three-dimensional memory device with high contact via density and methods of forming the same

A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to receive and store program page data and utilizing a second data latch to store bit information indicating which cells are to be targeted for the multi-stage programming. At each program stage, a respective program loop may be performed with respect to each threshold voltage distribution generated during a prior program stage to create two new threshold voltage distributions from the prior distribution.

Data latch programming algorithm for multi-bit-per-cell memory devices

A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.

Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same

A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.

An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.

Non-volatile memory with efficient signal routing

A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked.

Non-volatile memory with three dimensional stacked word line switches

A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells, where X>Y.

Non-volatile memory with efficient word line hook-up

To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

Non-volatile memory with different word line hook up regions based on pass through signals

A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Three-dimensional memory device with separated contact regions and methods for forming the same

A bonded assembly of a memory die and a logic die is provided. The memory die includes a memory array, a plurality of bit lines, and memory-side bit-line-connection bonding pads. The logic die includes sense amplifiers located in a sense amplifier region, and logic-side bit-line-connection bonding pads located within the sense amplifier region and bonded to a respective one of the memory-side bit-line-connection bonding pads. The sense amplifier region has an areal overlap with a respective first subset the plurality of bit lines in a plan view, while a second subset of the plurality of bit lines does not have an areal overlap with the sense amplifier region in the plan view.

Bonded assembly of a memory die and a logic die including laterally shifted bit-line bonding pads and methods of forming the same

A semiconductor structure includes a bonded assembly of a first semiconductor die including first metal bonding pads and a second semiconductor die including second metal bonding pads, and a capacitor structure including a first electrode, a second electrode, and a node dielectric. The first electrode includes first bonded pairs of metal bonding pads. The second electrode includes second bonded pairs of metal bonding pads. The node dielectric includes portions dielectric material layers laterally surrounding the metal bonding pads.

Capacitor structure including bonding pads as electrodes and methods of forming the same

Non-volatile memory with different use of metal lines in word line hook up regions

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Cupertino, CA, United States of America

Fumiaki Toyama