Sanyo Electric Co., Ltd.

Fumiaki Nagao

Koji Takano

Masato Fuma

Tomonori Kamiya

Miyuki Okamoto

Masaru Matsui

Yuji Sakai

A digital demodulation apparatus for performing a stable oscillation operation has a simple circuit configuration. The digital demodulation apparatus includes a pulse width counter for measuring a cycle of a modulated signal to generate digital cycle information. A first digital filter equalizes the digital cycle information to generate averaged cycle information. A comparator compares the digital cycle information and the averaged cycle information to generate a bi-phase signal. A phase-locked loop generates a clock signal having a frequency according to the averaged cycle information and a phase being synchronized with the phase of the bi-phase signal.

Digital demodulation apparatus

A method according to the present invention generates weight data for each audio band and assigns a number of bits to each band according to the weight data. The method then calculates a total of the numbers of bits of one block and compares the total with an upper limit and with a lower limit of a compression target value. Based on the comparison result, the method increases or decreases the value of the weight data to update it. The method reassigns a number of bits based on the updated weight data.

Method and apparatus for subband coding, allocating available frame bits based on changable subband weights

In a digital signal processor having an improved arithmetic processing efficiency, there is provided in parallel a first ROM for storing branch commands and a second ROM for storing arithmetic commands. The ROMs are connected to a branch command decoder and an arithmetic command decoder, respectively. Operations of a first memory control circuit and a second memory control circuit are controlled in response to instructions from the branch command decoder, while operations of an arithmetic circuit are controlled in response to instructions from the arithmetic command decoder. By processing the branch commands and the arithmetic commands in parallel, the operation efficiency of the arithmetic circuit is enhanced.

Digital signal processor

A digital filter is provided with a plurality of selectors. Switchover from one selector to another switches the digital filter operation between a separation filter function and a synthesis filter function. When the digital filter functions as either separation filter or synthesis filter, it switches over between the functions of multiplying data by a filter coefficient and multiplying data by an attenuation coefficient. The entire digital filter circuit size can thus be reduced.

Digital filters

The processing of a digital filter ( ) switches between the separation of audio data and the synthesis of a plurality of band data. An attenuator ( ), one end of which is connected to the digital filter ( ) and the other end is connected to the audio data input-output port, attenuates the input audio data and supplies it to the digital filter and attenuates and outputs the audio data that has been output from the digital filter ( ). The attenuator ( ) and the digital filter ( ) are commonly used for both data compression and data expansion processing and therefore the entire circuit size of an audio data compression/expansion apparatus is reduced.

Audio data compression/expansion apparatus and digital filter

A tracking servo circuit for stopping movement of a pickup device at a target position on a recording track of a recording medium, such as a CD, includes an A/D converter that generates error data from a tracking signal. The tracking error signal has a positive value when the pickup device is located at a first side of the recording track and a negative value when the pickup device is located on the opposite side of the recording track. The error data includes a code bit indicating the polarity of the tracking signal. A selector control circuit generates a selection signal using the code bit. A selector connected to the A/D converter and the selector control circuit selects either the error data or a fixed data value based on the selection signal. A drive signal generator receives the selected data and generates a drive signal to stop the radial movement of the pickup device.

Tracking servo circuit

Logarithm of data x being input is taken to calculate a decibel value y. The input value x is separated into mantissa value a and exponent value b by a separator or on the basis of an expression x&equals;a&middot;2 . Logarithmic value 10&middot;log a corresponding to the mantissa value a is read from ROM. The exponent value b is multiplied with a constant 10&middot;log 2 for logarithm of 2 by a multiplier. A logarithmic value of the value a read from the ROM is added to b&middot;10&middot;log 2 output from the multiplier by an adder to obtain the decibel value y. Thus, a simple circuit can compute the decibel value at a high speed.

Logarithmic value calculation circuit

A memory control circuit for writing or reading digital data at a high speed without increasing access speed to the memory circuit. The memory control circuit includes a control signal generation circuit for generating a first write enable signal and a first read enable signal of a first memory circuit, an address generation circuit for generating an address signal designating a data write address of the first memory circuit and a second memory circuit, and a write data supply circuit for supplying write data to the first and second memory circuits. A shift circuit is connected between the control signal generation circuit and the second memory circuit to generate a second write enable signal and a second read enable signal by shifting the first write enable signal and the first read enable signal by one cycle of a data write cycle or read cycle. The write data is written alternately to the first and second memory circuits in response to the first and second write enable signals. The data written to the first and second memory circuits is read alternately from the first and second memory circuits in response to the first and second read enable signals.

Dual memory control circuit

A digital filter is provided with a plurality of selectors. Switchover from one selector to another switches the digital filter operation between its separation filter function and synthesis filter function. The digital filter is constructed mainly with a multiplier, an accumulator, and an adder-subtracter which are commonly used to implement both separation and synthesis filters. When the digital filter functions as the separation filter, the input data is output as is to the external by selector switchover.

Nine memories (,) are provided, out of which five memories are made memories for the present processing. Meanwhile, the remaining four memories are made memories for receiving and storing data to be inputted during the processing. Then, the memories (,) which have accepted input data to be inputted at each duration of 1 sound group (SG) are switched to be used for processing, and the memories (,) which have been for processing are switched to be used for receiving input data, but a memory (,) which has stored the latest data in the memories for processing is left for processing. With this arrangement, memory capacity can be reduced.

Memory device

To encode data Y after separating the data Y into a scale factor SF, a word length, and a data value X. For this purpose, X&equals;Y&middot;&lcub;2,&minus;1&rcub;/SF is calculated. Here, a value of &lcub;2,&minus;1&rcub;/SFV with respect to a number of SFV and a number of SL, which are obtained by separating into SF&equals;SF&middot;2,, is stored in a ROM in advance. Then, input data Y is separated into a mantissa part Yr and an index part Ye and Ye is added to SFF. Then, the shifter,shifts Yr according to an additional result to obtain Ye&middot;2,&middot;2,. On the other hand, based on SF and WL, which are determined with respect to Y, a value of corresponding &lcub;2,&minus;1&rcub;/SFV is read from the ROM. Then, the shifted result is multiplied by the output from the ROM to obtain a data value X. Also, Y&equals;SF&middot;X/&lcub;2,&minus;1&rcub; is calculated and decoded. Inputted SF is divided into SFV and SFF. Based on the obtained SFV and inputted WL, a value of corresponding SFV/&lcub;2,&minus;&rcub; is read from the ROM. SFF is given as an index value for the inputted X. The result with the index value given and the output from the ROM are multiplied in a multiplier to calculate Y to decode.

Encoder and decoder

An output of a flip flop (,) at a first stage is connected to a D-input of a flip flop (,) at a second stage, and an inverted-output of the flip flop (,) is connected to a D-input of a flip flop (,) at a third stage. A reference clock BCK is supplied to the D-input of the flip flop (,), and an oscillation clock OCK is inputted to each T-input of the respective flip flops (,) to (,). An XOR of the reference clock BCK and an output signal Q,of the flip flop (,), and a logical product of an output signal Q,of the flip flop (,) and an output signal Q,of the flip flop (,) are used as a first comparison output PDU and a second comparison output PDD, respectively. With this arrangement, phase comparison can be achieved using a clock of any duty ratio.

Phase detector

A separation filter has a memory for storing sequential input data. A multiplier multiplies sequential input data, read from the memory, by a predetermined filter coefficient. An accumulator sequentially accumulates the multiplication result from the multiplier. A pair of registers alternately receive the accumulation result from the accumulator. An adder/subtracter adds or subtracts two accumulation results, obtained from the register pair, together or one from the other, and outputs the operation result as two pieces of sequential output data which are the sequential input data separated. In a synthesizing filter, an adder/subtracter adds or subtracts two pieces of sequential input data together or one from the other, a memory stores the operation result from the adder/subtracter, a multiplier multiplies the operation result, read from the memory, by a predetermined filter coefficient, and an accumulator sequentially accumulates the multiplication result from the multiplier, and outputs the accumulation result as sequential output data which is the two pieces of sequential input data synthesized.

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Gifu, Japan

Fumiaki Nagao