Fuji Electric Co., Ltd.

National Space Development Agency of Japan

Fumiaki Kirihata

Yoshikazu Takahashi

Takashi Kobayashi

Satoshi Kuboyama

Hiromu Haruki

Hideaki Kakiki

Saburo Tagami

Katuhiro Endo

Osamu Hashimoto

In a power MOSFET, on an Ndrain layeras a substrate, a second N base layerand a first Nbase layerare deposited in the order by epitaxial growth. In a surface portion of the layer, there are selectively formed a P base region, in a surface portion of which an Nsource regionis selectively formed. On a channel region in the P base region, a gate electrodeis formed with a gate insulator filmheld between. A source electrodeand a drain electrodeare formed on the Nsource regionand on the back of the substrate, respectively. The layeris made to have a thickness equal to or more than &#xbc; of that of the first Nbase layer, and an averaged impurity concentration between 1&#xd7;10/cmand 3&#xd7;10/cm. The thickness can be alternatively given as equal to or more than &#xbd; of a difference between the thickness x shown as x(&#x3bc;m)=V(V)/8 and that of the layer, where Vis an SEB(Single Event Burnout) voltage of the layer. This makes positive feed back hard to occur between latch-up of a parasitic npn transistor and dynamic avalanche near the substrate to enhance the SEB voltage, allowing the MOSFET to be applied to space use.

Semiconductor device having an SEB voltage suitable for use in space

A semiconductor device is manufactured by a jig. The jig includes a pair of flat heat spreading devices with flat heaters, and an enclosing device for surrounding an assembly of the semiconductor device situated between the heat spreading devices. An assembly of the semiconductor device includes a common electrode plate, semiconductor chips placed above the common electrode, metal contact terminal plates placed above the semiconductor chips, and solder sheets placed at least a portion between the semiconductor device and the common electrode and a portion between the semiconductor chip and the contact terminal plate. The assembly is held between the heat spreading devices, and a reducing gas is supplied to isolate the assembly from atmosphere. The heater plates attached to the heat spreading plates is heated to uniformly heat the solder sheets at a predetermined temperature, and the heater plates are pressed vertically at a predetermined temperature to bond the semiconductor chips to the common electrode plate or to the metal contact terminal plates under pressure. Thus, the heights of the metal contact terminal plates are aligned uniformly.

Apparatus for manufacturing semiconductor device and method of

A semiconductor device comprises a semiconductor substrate of a first conductive type with a low impurity density; a first region of a second conductive type; a second region of the first conductive type with a high impurity density formed in a surface of the first region; a third region of the second conductive type with a high impurity density; a gate insulating film formed on the surface of the first region intervening between an exposed surface of the semiconductor substrate and the second region; a gate electrode formed on the gate insulating film; a fourth region of the second conductive type opposite to the first region on the other surface of the semiconductor substrate; a fifth region of the first conductive type with a high impurity density which is opposite to the third region and adjacent to the fourth region; a first electrode commonly brought into contact with the first and second regions; a second electrode brought into contact with the second region and connected to the first electrode; and a third electrode commonly brought into contact with the fourth and fifth regions.

IGBT with freewheeling diode

Provided is a semiconductor device for power switching applications which utilizes a plurality of gate terminals provided in pressure contact with gate electrodes, the gate terminal/electrodes situated so as separate current flow therethrough at time of gate turn off into separate components, thereby reducing the transverse voltage drop of the gate electrode. In one embodiment, the invention is applied to a gate turn off (GTO) thyristor, and in another embodiment, towards a reverse conducting GTO thyristor.

Semiconductor device

In a gate turn-off thyristor having a plurality of gate turn-off thyristor segments, each having a four-layer upon pnpn structure, a resistance layer is interposed between the emitter layer and the cathode electrode of each segment. A voltage drop occurs across the resistance layer and this voltage drop prevents a current concentration to a specific segment especially at the last stage of a turn-off process, so that the current flows in the respective remaining segments is improved. The voltage drop has a function of shunting the anode current so that the shunted current flows into the gate. Accordingly, the currents flowing through the respective segments and the turn-off times of the respective segments are intended to be made uniform. Therefore, the controllable on-state current can be considerably increased.

Growing community of inventors

Kawasaki, Japan

Fumiaki Kirihata