Nec Corporation

Fumiaki Katano

Junko Morikawa

Hidemasa Takahashi

The field effect transistor includes (a) a plurality of drain finger electrodes, source finger electrodes and gate finger electrodes disposed in an active region on a semiconductor substrate so that each of the gate finger electrodes is sandwiched between each of the drain and source finger electrodes, (b) a source electrode pad for electrically connecting the source finger electrodes to each other, and (c) a gate electrode pad for electrically connecting the gate finger electrodes to each other, the gate electrode pad being disposed farther away from the active region than the source electrode pad. By disposing the gate electrode pad farther away from the active region than the source electrode pad, it is possible to arrange the source electrode pads at higher density, which is accompanied by a lesser number of source finger electrodes associated with each of the source electrode pads. Thus, it is possible to decrease source inductance, and avoid parasitic oscillation.

Field effect transistor including a plurality of electrode units

A schottky barrier junction gate type field effect transistor includes a buffer layer formed on a semi-insulating GaAs substrate and including at least an undoped GaAs crystalline layer, a first n-type GaAs crystalline layer of a first carrier concentration formed on the buffer layer, and a second n-type GaAs crystalline layer formed on the first n-type GaAs crystalline layer and having a second carrier concentration which is lower than the first carrier concentration. A gate electrode made of a Schottky barrier metal is formed on the second n-type GaAs crystalline layer, and a pair of ohmic electrodes are formed at opposite sides of the gate electrode separately from the gate electrode. A third n-type GaAs crystalline layer is formed under each of the pair of ohmic electrodes and has a third carrier concentration which is higher than the first carrier concentration, and a fourth n-type GaAs crystalline layer is formed between the third n-type GaAs crystalline layer and a region which is composed of the first and second n-type GaAs crystalline layers. The fourth n-type GaAs crystalline layer has a fourth carrier concentration which is not less than the first carrier concentration, and a thickness corresponding to a total thickness of the first and second n-type GaAs crystalline layers.

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Tokyo, Japan

Fumiaki Katano