Hitachi, Ltd.

Nagase Co., Ltd.

Hitachi Video Eng. Inc.

Hitachi Microcomputer Eng. Co.

Fumiaki Fujii

Hideo Nishijima

Toshiro Suzuki

Yutaka Akiyama

Isao Fukushima

Yoichi Sato

Kaneyuki Okamoto

Kazuo Yamakido

Kenji Nagai

Masataka Sekiya

Kanji Otsuka

Izuru Yamada

Minoru Uwai

Katsumi Sera

Tatsuya Nagasawa

Shiro Hagiwara

Takashi Furutani

The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.

Semiconductor device and method of writing/reading entry address into/from semiconductor device

A still picture reproducing system for a magnetic recording and reproducing apparatus is disclosed. The system sends one frame in order to shift a reproduction mode from ordinary reproduction to reproduction of a still picture by use of so-called 'fine slow', sends one more frame if a noise is detected on a picture at this time, and stops if no noise is detected.

Still picture recording system with noise detection and frame counting

An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal of a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.

Integrated circuit having input and output terminals for testing

A retrieval signal recording apparatus for magnetic recording/reproducing apparatus wherein when an information signal is recorded on a magnetic tape, a retrieval signal different from the information signal is recorded at the beginning of the recorded information signal so that the magnetic tape is stopped or made in the reproducing mode just when the retrieval signal is picked up from the tape under a high tape speed. In the retrieval signal recording apparatus, the retrieval signal is recorded for a certain time only at the beginning of recording the signal or at both the beginning and end of the recorded signal, and the recording time of the retrieval signal is changed in accordance with the switching of a plurality of tape speeds such that the length of the retrieval signal recorded on the magnetic tape is made substantially constant even if the tape speed is different.

Retrieval signal recording apparatus for magnetic tape

An amplifier comprising a pair of differential input MISFETs, a current mirror circuit connected between the drains of the differential input MISFETs and a power source terminal, a phase compensation circuit connected to the drain of one of the differential input MISFETs, an output stage amplification circuit amplifying the signal produced at the drain of one of the differential input MISFETs, a phase regulation circuit such as a capacitor connected to the other of the differential input transistors, and a feedback circuit feeding back the output signal produced from the output stage amplification circuit to the other of the differential input MISFETs in order to apply negative feedback to the amplifier. Since the capacitor is provided, the phase of the power source noise can be made substantially equal to the phase of noise occurring at the drain of one of the differential input MISFETs due to the power source noise. Hence, hardly any noise is produced from the output stage amplification circuit. Since feedback is applied to the amplifier, the noise occurring at the drain of the other of the differential input MISFETs operates in such a manner as to limit the amount of change of the drain voltage of one of the differential input MISFETs due to the noise. As a result, a large change of the output signal due to the power source noise can be prevented. Furthermore, since an element to be added for this purpose may be merely a capacitor, a significant increase in the number of circuit elements can be avoided.

Amplifier having a high power source noise repression ratio

In a PCM encoder, in order to reduce noise in an idle channel or in the absence of any voice signal, a detector circuit is provided which detects the idle channel, and a circuit is connected to the detector circuit which fixes the polarity bit of the PCM signal produced by the PCM encoder when the detector circuit has detected the idle channel.

PCM Encoder conformable to the A-law

Growing community of inventors

Tokyo, Japan

Fumiaki Fujii