Intel Corporation

Texas Instruments Corporation

Fulvio Spagna

Debendra Das Sharma

Venkatraman Iyer

Robert G Blankenship

Darren S Jue

Ashish Gupta

Jeffrey Charles Swanson

Shenggao Li

Rahul R Shah

Sitaraman V Iyer

Arvind A Kumar

Raj K Ramanujan

Yen-Cheng Liu

Simon P Johnson

Robert J Safranek

Herbert H Hum

Vedaraman Geetha

Bahaa Fahim

Aaron T Spink

Robert H Beers

Jeff Willey

William Harry Nale

Abhishek Das

Yuvraj S Dhillon

Robert A Maddox

Wenyan Vivian Jia

Michelle C Jen

Bruce A Tennant

Guluke Tong

Minxi Gao

Noam Dolev Geldbard

Daniel S Froelich

Sujatha Gowder

Per E Fornberg

David Edward Bradley

Robert Bogdan Staszewski

William R Halleck

Shin Chung Chen

Ji Chen

Michael V De Vita

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface

Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface

There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

In-band margin probing on an operational interconnect

An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.

High speed interconnect with channel extension

Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.

High performance interconnect physical layer

Recalibration of PHY circuitry for the PCI Express (PIPE) interface based on using a message bus interface

There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the Lstate. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase error information based on the input signal. A first circuit path provides proportional control information based on the data information and phase error information. A second circuit path provides integral control information based on the data information and phase error information. The first circuit path operates at a frequency higher than the second circuit path. The DCO generates a clock signal and controls the timing of the clock signal based on the integral control information and the proportional control information.

Programmable clock data recovery (CDR) system including multiple phase error control paths

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Phase frequency detector

Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). In embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.

Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO)

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San Jose, CA, United States of America

Fulvio Spagna