Shanghai Huali Microelectronics Corporation

Fulong Qiao

Pengkai Xu

Yi Bin Wang

Yu Huang

Liyuan Liu

Xiao Yang

Li He

Jia Ren

Wenyan Sun

Limin Zhou

The disclosure provides a method for manufacturing shallow trench isolations, providing a substrate comprising a storage cell area and a peripheral area of a storage device; etching the upper part of the substrate of the storage cell area using a first etching process to form a first shallow trench, and filling the first shallow trench with silicon oxide using a first deposition process; and etching the upper part of the substrate of the peripheral area using a second etching process to form a second shallow trench, and filling the second shallow trench with silicon oxide using a second deposition process; wherein the depth and characteristic dimension of the first shallow trench are smaller than the depth and characteristic dimension of the second shallow trench. The disclosure can avoid the silicon dislocation defect of the peripheral area and ensure the device shape and characteristic dimension of the storage cell area.

Method for manufacturing shallow trench isolations

The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.

Semiconductor device and method for manufacturing the same

The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield.

Semiconductor device and manufacturing method thereof

A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.

Gate structure and photomask of NAND memory and method for making the same

The present invention provides a semiconductor structure and method of manufacturing the same. The semiconductor structure includes a substrate and a gate formed on the substrate. The above manufacturing method is used to form a gate on the substrate. The above manufacturing method specifically includes: providing a substrate; forming a trench in an upper portion of the substrate; depositing a gate layer on the substrate, the gate layer including two step portions extending from the outside of the trench to the inside of the trench; etching the gate layer from two ends of the trench along the two step portions toward the center of the trench to form the gate in the trench, wherein the width of the gate is smaller than the width of the trench. The manufacturing method of the present invention can easily and efficiently form a gate having a small critical dimension and precisely controllable on a semiconductor substrate, thereby meeting increasingly stringent gate size requirements.

Semiconductor structure and method of manufacturing the same

A manufacturing method of a Flash wafer, comprises: fabricating a Flash wafer containing a cell area, a logical area and a capacitance area; adjusting the height of the silicon oxide filled shallow trench in the logical area and the capacitance area; sequentially depositing a silicon nitride layer and a silicon oxide layer on the upper surface of the Flash wafer, and sequentially removing the silicon oxide layer and the silicon nitride layer on the upper surface of the cell area and on the upper surface of the floating gate in the logical area and the capacitance area; adjusting the height of the silicon oxide filled shallow trench in the cell area and the capacitance area; depositing an interlayer dielectric layer on the surface of the Flash wafer; removing the rest part in the logical area by protecting the cell area and the capacitance area with a mask.

Growing community of inventors

Shanghai, China

Fulong Qiao