Renesas Technology Corp.

Hitachi, Ltd.

Fukuo Owada

Takashi Aoyama

Kozo Watanabe

Masaaki Shinohara

Masataka Kato

Yoshiaki Kamigaki

Shinichi Minami

Hideki Yasuoka

Masahito Takahashi

Akihiko Satoh

Shiro Akamatsu

A semiconductor device having a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, the transistors each including a gate insulating film formed over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the corresponding gate electrode. Sidewall spacers of the first field effect transistor are different from those of at least the second field effect transistors. Also, the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor and the gate electrode of the third field effect transistor has a length different from that of either the first field effect transistor or second field effect transistor. The sidewall spacers of the first field effect transistor include a first silicon oxide film, a first silicon nitride film over the first silicon oxide film and a second silicon oxide film over the first silicon nitride film.

Semiconductor device with rewritable nonvolatile memory cell

Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the gate electrode associated with each of the first through third field effect transistors. The sidewall spacers of at least the first field effect transistor have a different width than that of at least the second field effect transistor, the gate electrode of the third field effect transistor has a different length than that of at least the first field effect transistor for memory and the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor.

Semiconductor device and a method of manufacturing the same

A method of manufacture of a semiconductor device uses simplified steps while improving the electrical properties of each element in the semiconductor device. Over a semiconductor substrate, having a memory gate electrode, control gate electrode and gate electrode formed thereover, a silicon oxide film, a silicon nitride film and a silicon oxide film are formed successively. The silicon oxide film formed over the gate electrode is then removed by wet etching. The silicon oxide film, silicon nitride film and silicon oxide film formed over the semiconductor substrate are removed successively by anisotropic dry etching, whereby respective sidewall spacers having a relatively large width and a relatively small width are formed.

Method of manufacture of a semiconductor device

A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.

Method of manufacturing a semiconductor integrated circuit device

A plurality of connection holes for connecting n type semiconductor region of zener diodes (D , D ) and wires and to each other are not arranged in the center of the n type semiconductor region , that is, in a region in which a p type semiconductor region and the n type semiconductor region form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes are spaced from each other so that a pitch between the adjacent connection holes is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes are formed by means of dry etching.

Semiconductor integrated circuit device and method of manufacturing the same

A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode. A hole for connecting between the two layers of the gate electrode of a first field-effect transistor used as perpheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting between the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.

method for forming capacitors and field effect transistors in a semiconductor integrated circuit device

A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells. A hole for connecting the two layers of the gate electrode of a first field-effect transistor used as peripheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.

Growing community of inventors

Ome, Japan

Fukuo Owada