Fujitsu Corporation

Fujio Ikegami

Saburo Kaneda

Kazuyuki Shimizu

Naomi Matsumura

Masamichi Ishibashi

Takamitsu Tsuchimoto

Yukichi Ikuta

Yoshikatsu Seta

When input data composed of a symbol string is compressed, bit maps are used. In each bit map, '1' is set to a bit that represents the position of a relevant symbol of the symbol string. In contrast, '0' is set to a bit that represents the position of another symbol of the symbol string. When compressed data is expanded, symbols are expanded in the order thereof. Thus, the positions of symbols that have been expanded are omitted from each bit map. Consequently, each bit map can be shortened and thereby the compression ratio can be improved. Since the length of each bit map is variable, a value of which (the number of symbols expanded by corresponding bit map-2) is added as information for expanding symbols from each variable bit map of the compressed data correctly. In addition, to distinguish data having a bit map from data having no bit map, a flag that represents the presence of a bit map is added to the compressed data.

Data compressing method and apparatus to generate bit maps in accordance

A virtual machine system having a virtual storage function, wherein registers are provided for holding the heading and trailing addresses of the continuous area in the main storage area assigned respectively for each of the plural operating systems. When the main storage area is accessed by a channel or sub-channel, one of the registers is selected, and the heading address of the register selected is added to the main storage address sent from the channel or sub-channel. The added main storage address is compared with the trailing address in the selected register and if the former is smaller than the latter, the overhead for supporting the virtual storage area is reduced by accessing the main storage area in accordance with the added main storage address mentioned above.

Channel address control system for a virtual machine system

Virtual machine system

An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.

Address control system for software simulation

Growing community of inventors

Yokohama, Japan

Fujio Ikegami