Axis Semiconductor, Inc.

Ericsson Evdo Inc.

Fugui Wang

Xiaolin Wang

Qian Wu

Ke Ning

Benjamin Marshall

Gregory Steve Pitarys

Gopal Harikumar

Deepak Garg

Gregory Pitarys

A connection is established between an access terminal and a first radio network controller through a first radio node. The first radio node is controllable primarily by the first radio network controller. The connection is maintained with the first radio network controller as the access terminal moves from a coverage area of the first radio node toward a coverage area of a second radio node. The second radio node is controllable primarily by a second radio network controller and controllable subordinately by the first radio network controller. A connection is also established through the second radio node. Upon a fulfillment of a predetermined criterion, the connection is transferred from the first radio network controller to the second radio network controller.

Handing off active connections

Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Instruction set design, control and communication in programmable microprocessor cores and the like

The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions

Growing community of inventors

Sterling, MA, United States of America

Fugui Wang