Mstar Semiconductor, Inc.

Mediatek Corporation

Fucheng Wang

Chao-Tung Yang

Yi Wei Lu

Tao Chen

Tsang-Wei Yu

Mingchun Chiang

Jun Ma

Wen Yang Chou

Yao-Chi Wang

Heng-Chih Lin

Shuo-Yuan Hsiao

Jian-Yu Ding

Hsu-Hung Chang

Shuo Yuan Hsiao

Chung-Yun Chou

Shen-Ching Sun

Various examples with respect to synchronization signal block (SSB) raster shift in mobile communications are described. A processor of a user equipment (UE) performs an initial cell search to identify a cell among one or more cells of a wireless communication system. The processor then camps on the identified cell. In performing the initial cell search, the processor scans through a plurality of SSB entries for frequency bands below 3 GHz with a SSB raster spacing and a SSB raster offset frequency that support sub-carrier spacing (SCS) spaced channel raster and 100 kHz channel raster for both 15 kHz SCS and 30 kHz SCS. A minimum channel bandwidth at 5 MHz or higher for 15 kHz SCS or at 10 MHz or higher for 30 kHz SCS is supported. The SSB raster spacing is a common multiple of 15 kHz and 100 kHz. The SSB raster offset frequency for 100 kHz channel raster is a multiple of 30 kHz plus/minus 10 kHz.

Synchronization signal block raster shift in mobile communications

A tuner includes a plurality of paths, and at least one of the paths includes a front-end filter circuit, an amplifier, and a trace filter. The trace filter includes a varactor and an inductor, which are coupled to an output end of the amplifier. Further, the amplifier and the varactor of the tuner are packed in a complementary metal-oxide semiconductor (CMOS) chip.

Tuner and front-end circuit thereof

The present invention discloses a frequency synthesizer which includes: a PLL including an oscillator for generating an oscillator signal and a first frequency divider for dividing a frequency of the oscillator signal to generate a first frequency-divided signal; a switching unit for switching the PLL to either an open loop status or a closed loop status; a second frequency divider, for dividing a frequency of a reference clock to generate a second frequency-divided signal; a counter, for counting according to the first frequency-divided signal and the second frequency-divided signal to generate a counter value when the PLL is in the open loop status; a comparator, for comparing the counter value with a predetermined value to generate a comparing result; and a determining unit, for adjusting an oscillator frequency of the oscillator according to the comparing result.

Frequency synthesizer

A transmitting apparatus operative at a plurality of different bands includes at least a modulator, an intermediate frequency (IF) filter, and an offset phase-locked-loop (OPLL). Regardless at which one of the frequency bands the transmitting apparatus operates, a divisor of at least one frequency divider included within the OPLL is fixed, and a signal, which is outputted by a controllable oscillator and received by an offset mixer included within the OPLL, corresponds to a substantially fixed frequency.

Transmitting apparatus operative at a plurality of different bands and associated method

An analog television (TV) receiver converts a received analog TV signal to a digital TV signal and performs digital demodulation to increase demodulation efficiency. The analog TV receiver includes a radio frequency (RF) turner and an intermediate frequency (IF) circuit. The RF tuner converts the received analog RF TV signal to an analog IF TV signal. The IF circuit includes a converting circuit and a digital demodulator. The converting circuit converts the analog IF TV signal to a digital TV signal. The digital demodulator demodulates the digital TV signal to generate a digital demodulated video signal and a digital demodulated audio signal.

Analog television receiver for processing intermediate frequency TV signal

A television tuner employs a triple-conversion architecture to translate VHF/UHF TV signals to various standard IF frequencies. The television tuner includes a harmonic rejection mixer, a first image rejection mixer and a second image rejection mixer. The television tuner receives a television signal. The harmonic rejection mixer up-converts the television signal into a first IF signal according to a first reference signal with a fixed frequency. The first image rejection mixer further up-converts the first IF signal into a second IF signal according to a second reference signal with a tunable frequency. The second image rejection mixer down-converts the second IF signal into a third IF signal according to a third reference signal with a tunable frequency.

Triple-conversion television tuner

A television tuner employs a single down-conversion architecture to translate VHF/UHF TV signals to various standard IF frequencies. The television tuner includes a harmonic rejection and quadrature mixer and a quadrature mixer. The harmonic rejection and quadrature mixer mixes a first-band signal with a reference signal to output a first pair of in-phase and quadrature-phase signals with a harmonic-frequency component eliminated from the resulting signals. A quadrature mixer mixes a second-band signal with the reference signal to output a second pair of in-phase and quadrature-phase signals. A digital signal processing circuit coupled to both the harmonic rejection and quadrature mixer and the quadrature mixer for selectively processing either the first pair of in-phase and quadrature-phase signals or the second pair of in-phase and quadrature-phase signals to generate an output signal corresponding to a desired channel.

Single down-conversion television tuner

A television tuner employs a double quadrature mixing architecture to frequency-translate VHF/UHF TV signals to various standard IF frequencies. In the television tuner, a quadrature mixer converts the input television signal into a first in-phase signal and a first quadrature-phase signal according to a first reference signal, and a double quadrature mixer converts the first in-phase signal and first quadrature-phase signal into a second in-phase signal and a second quadrature-phase signal according to a second reference signal, and a polyphase filter filters the second in-phase signal and second quadrature-phase signal to produce an output signal.

Television tuner with double quadrature mixing architecture

A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current.

Transconductor having high linearity and programmable gain and mixer using the same

A sign detection device including a first comparing device for comparing a first input signal with a first threshold signal in a first period and a second period to generate a first output signal; a second comparing device for comparing a second input signal with a second threshold signal to generate a second output signal; a converter for optionally changing the polarity of the second output signal to obtain a third output signal; and an operator coupled to the first comparing device and the converter for performing a logic operation of the first output signal and the third output signal to obtain polarity information of the product of the first input signal and the second input signal.

Sign detection device and associated method

A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal. The predetermined divider cell corresponds to the determination result.

Multi-modulus divider with extended and continuous division range

A method for tuning a tunable filter includes inputting a control signal to the tunable filter and tuning the configuration of the tunable filter according to the control signal. When the control signal is at any one of a plurality of predetermined states, a step size of a characteristic frequency of the tunable filter is positively correlated with the characteristic frequency of the tunable filter.

Method for tuning a tunable filter

A delta-sigma modulated fractional-N PLL frequency synthesizer is provided. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal; a charge pump for generating an output current pulse in response to the phase difference signal; a loop filter for filtering the charge pump output current pulse and generating a corresponding control voltage; a VCO for generating a VCO output signal with a voltage controlled frequency (Fvco) in response to the control voltage; and a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an integer input terminal, for determining the ratio of the VCO frequency (Fvco) and the reference frequency (Fref).

Growing community of inventors

San Jose, CA, United States of America

Fucheng Wang