Stmicroelectronics Gmbh

Texas Instruments Corporation

Stmicroelectronics Asia Pacific Pte Limited

Stmicroelectronics (grenoble) Sas

Fuchao Wang

Ming Fang

Ravi Shankar

Olivier Le Neel

Olivier Leneel

Hai Ding

William David French

Pinghai Hao

Dok Won Lee

Chengyu Charles Niu

Duofeng Yue

Jonathan Philip Davis

Neal T Murphy

Brian E Zinn

Yousong Zhang

Pascale Dumont-Girard

Prakash Dalpatbhai Dev

Zhiyong Xie

Michel Arnoux

Ricky A Jackson

Nicholas Andrew Kusek

Billy Alan Wofford

Dina Rodriguez

Dongping Zhang

Christopher Eric Brannon

Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

Thin film anisotropic magnetoresistor device and formation

An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Closed loop temperature controlled circuit to improve device stability

An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.

Magnetic core for integrated magnetic devices

An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

Heating system and method for microfluidic and micromechanical applications

Method to form magnetic core for integrated magnetic devices

An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.

Integrated anisotropic magnetoresistive device

In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.

Methods and apparatus for preventing counter-doping during high temperature processing

A method includes: growing a oxide layer on a topside of a semiconductor wafer using a local oxidation of silicon (LOCOS) process; forming a photoresist pattern with an alignment opening on the oxide layer; etching the oxide layer to form a trench in the oxide layer; etching an alignment mark trench into the exposed surface of the semiconductor wafer; depositing a dielectric layer that is one of a silicon nitride material or a silicon oxynitride material; performing an anisotropic plasma etch to remove the dielectric layer from horizontal surfaces on the oxide layer and the alignment mark trench and to form sidewalls from the dielectric layer on vertical sidewalls of the alignment mark trench; growing an alignment mark oxide layer on a bottom surface of the alignment trench; and etching and removing the oxide layer and the alignment mark oxide layer.

Methods and apparatus for alignment marks

An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

Single photomask high precision thin film resistor

Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.

Method to reduce metal fuse thickness without extra mask

Growing community of inventors

Plano, TX, United States of America

Fuchao Wang