Micron Technology Incorporated

Fuad Badrieh

Thomas H Kinsley

Baekkyu Choi

Brent Keeth

Adam Saleh El-Mansouri

Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.

Predictive power management

Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

Dynamic allocation of a capacitive component in a memory device

A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.

Feedback for power management of a memory die using a dedicated pin

Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

Sensing and tuning for memory die power management

Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

Power management for a memory device

Methods, systems, and devices for varying a time average for feedback of a memory system are described. An apparatus may include a voltage supply, a memory array, and a regulator coupled with the voltage supply and memory array and configured to supply a first voltage received from the voltage supply to the memory array. The apparatus may also include a voltage sensor configured to measure a second voltage of the memory array and a digital feedback circuit coupled with the memory array and regulator and configured to generate feedback comprising information averaged over a duration based at least in part on the second voltage measured by the voltage sensor and to transmit an analog signal to the regulator based at least in part on the feedback.

Varying a time average for feedback of a memory system

Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

Memory device power management

A voltage of a conductive line, such as a control line, a data line, or a voltage supply line associated with a memory die may be monitored. A frequency response of the voltage may be analyzed to determine if the conductive line may be operating at or near a specific frequency, such as a resonance frequency. If the conductive line is operating at or near the specific frequency, an action, such as a memory operation, may be performed to mitigate the resonance of the conductive line. The monitoring, analyzing, and action performing may be accomplished with circuitry of the memory die.

Voltage resonance mitigation of memory dies

Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

Feedback for power management of a memory die using shorting

A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

Feedback for power management of a memory die using capacitive coupling

Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.

Growing community of inventors

Boise, ID, United States of America

Fuad Badrieh