Weltrend Semiconductor Inc.

Fu-Yuan Hsiao

Ke-Ning Pan

Shih-Tsung Kuo

The configuration of an apparatus for automatically calibrating a clock of a non-crystal oscillator and method thereof are disclosed. The proposed method for automatically calibrating the clock of the non-crystal oscillator includes sending a NACK signal to a host and fine-tuning the clock of the non-crystal oscillator via a frequency calibration system for non-crystal oscillator when a USB device receives an in-token command from the host, and outputting a datum from the USB device to the host.

Apparatus for automatically calibrating clock of non-crystal oscillator and method thereof

Generate a series of digital data according to a pair of differential signals received from a low speed universal serial bus. Calibrate coarsely a frequency of an oscillator according to a width of an end-of-packet of the series of digital data. And calibrate finely the frequency of the oscillator according to a width of a SYNC pattern of the series of digital data.

Frequency calibration circuit for automatically calibrating frequency and method thereof

The present invention provides a pixel clock generator for automatically adjusting the horizontal resolution of an OSD screen. The OSD screen is displayed on a displaying device, the displaying device comprises a screen and a display control circuit for displaying an image frame on the screen according to an incoming horizontal synchronous signals and horizontal image signals. The image frame comprises a plurality of horizontal image lines. Each of the horizontal image signals are used for forming one of the horizontal image lines of the image frame, and each of the horizontal synchronous signals comprises a scan signal and a retrace signal. The pixel clock generator comprising a phase locked loop (PLL) circuit and an adjusting circuit. The adjusting circuit has a control port for receiving a multiplier wherein the PLL circuit generates a quantity of the pixel clocks approximately equal to the multiplier within the receiving time period of each of the horizontal synchronous signals. The adjusting circuit has three input ports for receiving a predetermined horizontal resolution value, the horizontal synchronous signals, and the pixel clocks generated by the PLL circuit. The adjusting circuit generates the multiplier fed into the control port of the PLL circuit according to the inputs from the three input ports to make the quantity of the pixel clocks generated by the PLL circuit within the receiving time period of each of the scan signals approximately equal to the horizontal resolution value.

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Hsinchu, Taiwan

Fu-Yuan Hsiao