Macronix International Co., Ltd.

Fu-Tsang Wang

Chun-Hsiung Hung

Shuo-Nan Hung

Ji-Yu Hung

Shih-Lin Huang

Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

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Kaohsiung, Taiwan

Fu-Tsang Wang