Industrial Technology Research Institute

Harris Corporation

David Sarnoff Research Center, Inc.

Electronics Research & Service Org.

Fu-Lung Hsueh

Andrew G Dingwall

A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks. In other embodiments of the invention the ADC is implemented in CMOS technology and the pseudocomparators use ratioed transistor widths and ratioed capacitors to proportionally divide the output signals of the actual comparators in order to generate the interstitial output values. A final embodiment of the invention combines two averaging flash ADCs to form a novel subranging ADC.

Averaging flash analog-to-digital converter

A twelve bit analog-to-digital converter uses two banks of 31 capacitors each coupled through separate control circuitry to a five bit analog-to-digital converter with plus or minus 1/2 bit accuracy and two separate eight bit analog-to-digital converters each having plus or minus 1/2 bit accuracy to achieve a frequency of operation from at least several MHz to up to about 40 MHz.

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Plainsboro, NJ, United States of America

Fu-Lung Hsueh