Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

National Taiwan University

Fu-Lung Hsueh

Chewn-Pu Jou

Chan-Hong Chern

Chih-Chang Lin

Ming-Chieh Huang

Hsieh-Hung Hsieh

Tsung-Ching Huang

Shine Chung

Chien-Hsun Lee

Yi-Hsuan Liu

Tzu-Jin Yeh

Ho-Hsiang Chen

Shine Chien Chung

Tao Wen Chung

Sa-Lly Liu

Ming Hsien Tsai

Calvin Yi-Ping Chao

Ming-Hsien Tsai

Jiun Yi Wu

Jiun-Yi Wu

Yuwen Swei

Honyih Tu

Yung-Chow Peng

Huan-Neng Chen

Kuo-Yu Chou

Ying-Ta Lu

Kuang-Kai Yen

Tao-Wen Chung

Po-Yao Ke

Po-Yi Wu

Chi-Feng Huang

Clement Hsingjen Wann

Chih-Hsin Ko

Chao-Ching Cheng

Shang-Ying Tsai

Chun-Chieh Lu

Jun-De Jin

Shen-Iuan Liu

Mingo Liu

Nang-Ping Tu

Po-Wen Chiu

Bryan David Sheffield

Harry-Hak-Lay Chuang

Alexander Kalnitsky

Li-Chun Tien

Jhy-Jyi Sze

Ya-Chen Kao

Chih-Ping Chao

Hsien-Yuan Liao

Chun-Jung Lin

Sung-Chieh Lin

Wei-Li Chen

Yen-Jen Chen

Tong-Chern Ong

Chih-Min Liu

Chi-Hsien Lin

Sally Liu

Yung-Hsu Chuang

Ping-Lin Yang

Tsung-Hsiung Lee

Fan-ming Kuo

Tsung-Hsiung Li

Shih-Hung Lan

Shi-Hung Wang

Fu-Chieh Hsu

I-Fey Wang

Kuo-Tung Sung

Hung-Jen Liao

Chuei-Tang Wang

Hsiao-Tsung Yen

Han-Ping Pu

Jaw-Juinn Horng

Yi-Kan Cheng

Chih-Hsien Chang

Feng Wei Kuo

Lan-Chou Cho

Kuoyuan (Peter) Hsu

Feng-Wei Kuo

Jui-Jen Wu

Ming-Hsiang Song

Yu-Ling Lin

Denny Tang

William Wu Shen

Szu-Lin Liu

Sen-Kuei Hsu

Yung-Lung Lin

Shang-Fu Yeh

Tzong-Lin Wu

Po-Hung Chen

Tsung-Ching (Jim) Huang

Jiann-Tseng Huang

Chiang Pu

Chin-Yi Lin

Ming-Tsun Lin

Chu-Fu Chen

Yi-Che Chen

Chien-Min Lin

Yang-Chih Huang

Shu Yi Ying

Wei Lun Tao

A method of making a semiconductor device includes forming a first transmission line over a substrate. The method includes forming a second transmission line over the substrate. The method further includes depositing a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material partially covers each of the first transmission line and the second transmission line. The method further includes depositing a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material directly contacts the first transmission line or the second transmission line.

Semiconductor device and methods, where first and second transmission lines are surrounded by first and second high-k dielectric materials

An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.

Interconnect structure having conductor extending along dielectric block

A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.

Thermocouple device

An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.

A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.

Method of using varainductor having ground and floating planes

A semiconductor device includes a first transmission line. The semiconductor device includes a second transmission line. The semiconductor device includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material partially covers each of the first transmission line and the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material directly contacts each of the first transmission line and the second transmission line.

Semiconductor device and method, where a dielectric material directly contacts a high-k dielectric material and first and second transmission lines

An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.

A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.

Varainductor having ground and floating planes and method of using

A semiconductor device includes a first transmission line and a second transmission line. The semiconductor device further includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material surrounds the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material is separated from the first transmission line and the second transmission line.

Semiconductor device having a high-k dielectric material disposed beyween first and second transmission lines and a dielectric directly contacting the high-k dielectric material

A semiconductor device and method of making same are disclosed. In some embodiments, a method includes: forming a first thermoelectric conduction leg on a substrate; forming a second thermoelectric conduction leg on the substrate to be aligned with the first thermoelectric conduction leg along a same row; forming at least one intermediate thermoelectric conduction structure on an end of the second thermoelectric conduction leg; forming a contact structure to couple the first and second thermoelectric conduction legs via the at least one intermediate thermoelectric conduction structure; and recessing the substrate to form at least one trench substantially adjacent to a respective side edge of either the first thermoelectric conduction leg or the second thermoelectric conduction leg.

A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.

Input/output circuit and method

A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.

Capacitor having multiple graphene structures

A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.

A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.

Interconnect structure and method of manufacturing the same

A varainductor includes a signal line, a ground plane, and a floating plane over a substrate. The ground plane is disposed on a side of the signal line, and the first floating plane is disposed between the ground plane and the signal line. An array of switches includes at least two switches configured to selectively electrically connect the ground plane to the floating plane.

Varainductor having ground and floating planes

Growing community of inventors

Kaohsiung, Taiwan

Fu-Lung Hsueh