Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

National Applied Research Laboratories

Vanguard Semiconductor Corp.

Fu-Liang Yang

Yee-Chia Yeo

Chenming Hu

Hao-Yu Chen

Chien-Chao Huang

Tzyh-Cheang Lee

Erik S Jeng

Chao-Hsiung Wang

Chang-Yun Chang

Chun-Sheng Liang

Jiunn-Ren Hwang

Hung-Wei Chen

Kuo-Nan Yang

Chun-Chieh Lin

Tsung-Lin Lee

Wei-Ray Lin

Ping-Kun Wu

Bih-Tiao Lin

Cheng-Chuan Huang

Mong-Song Liang

Hou-Yu Chen

Sheng-Da Liu

Yi-Ling Chan

Carlos H Diaz

Ping-Wei Wang

Hsun-Chih Tsao

Ming-Hong Kuo

Chen Ming Hu

Chung-Ju Lee

Shih-Chang Chen

Wen-Chin Lee

Liang-Gi Yao

Yi-Ming Sheu

Hung-Ming Chen

Fang-Shi Jordan Lai

Di-Hong Lee

Tang-Xuan Zhong

Tien-Chih Chang

Tone-Xuan Chung

You-Lin Chu

ChiaHua Ho

Chia-Shiung Tsai

Syun-Ming Jang Jang

Hun-Jan Tao

Lan-Lin Chao

Hsin-Hui Lee

Chia-Hui Lin

Tzu-Shih Yen

Bi-Ling Chen

Tzu-shih Yen

Bin Liu

Haur-Ywh Chen

Chih-Yang Lin

Chun Chieh Lin

Yi-Lang Chen

How-Yu Chen

Chanming Hu

Tseung-Yuen Tseng

Chun Chich Lin

Andrew Yeh

Alex Chang

Sung-Pi Tseng

Ming-Yi Yang

Denny Duan-Iee Tang

Horng-Huei Tseng

Chi-Ming Yang

Kuang-Hsin Chen

Min-Hwa Chi

Ing-Ruey Liaw

Chao-Ming Koh

Fang-Cheng Chen

Ju-Wang Hsu

Baw-Ching Perng

Yin Jen Chen

Yin-Pin Wang

Chung-Hu Ge

Tony Liang-Tung Chang

Yu-Sheng Lai

Hao-Chieh Liu

Chun-Chi Chen

Wan-Yih Lien

Liang-Tung Tony Chang

Hsien-Chang Chang

Szu-Hung Chen

Yu-Chun Ho

Hsu-Li Cheng

I-Ping Lee

Tzu-Ying Chen

Shyi-Long Shy

Wen-Jya Liang

Cheng-Kuo Wen

I-Fang Cheng

Cheng-Chung Huang

Chien-Sheng Hsieh

Cheng-San Wu

Yuh-Sheng Chern

Chan-Jen Kuo

Hung-Min Chen

Chi Min-Hwa

Tim Tsao

An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Diode array for connecting to phase change memory and method forming same

Phase change memory with diodes embedded in substrate

FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.

FinFET device for device characterization

A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

CMOS device with raised source and drain regions

A bio-chip adapted for separating and concentrating particles in a solution includes a chip body defining a receiving space therein for receiving the solution, an inner electrode disposed in the receiving space, an outer electrode unit disposed in the receiving space of the chip body and including a first outer electrode that is spaced apart from and surrounds the inner electrode, and a second outer electrode that is spaced apart from and surrounds the first outer electrode, and a power source electrically connected to the inner electrode, the first outer electrode, and the second outer electrode. A method for using the bio-chip to separating and concentrating the particles in the solution is also disclosed in the present invention.

Bio-chip and method for separating and concentrating particles using the same

A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

FinFET for device characterization

A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

Structure for a multiple-gate FET device and a method for its fabrication

A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.

Methods of forming phase change memory with various grain sizes

A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.

Method of fabricating a resistive non-volatile memory device

An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.

Fully depleted SOI multiple threshold voltage application

A semiconductor light emitting device and a method to form the same are disclosed. The device has at least one porous or low density dielectric region formed in or on top of a bottom electrode, at least one top electrode on the porous or low density dielectric region, and one or more color filters placed above the top electrode, wherein the porous or low density dielectric region contains light emitting nanocrystal materials.

Programming optical device

Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.

Strained gate electrodes in semiconductor devices

Growing community of inventors

Hsin-Chu, Taiwan

Fu-Liang Yang