Macronix International Co., Ltd.

Skymedi Corporation

Fu-Chia Shone

Shin-Jang Shen

Chun-Hsiung Hung

Ming-Hung Chou

Ray-Lin Wan

Tom D Yiu

Jyh-Chyurn Guo

Tzeng-Huei Shiau

Hsin-Chien Chen

A memory structure formed between two doping regions in a semiconductor substrate includes two conductive blocks functioning as floating gates formed at two sides of a first conductive line functioning as a select gat and insulated from the first conductive line with two first dielectric spacers therebetween, wherein the two conductive blocks each have a raised top and raised parts of sides relative to the top of the first conductive line. A first dielectric layer is formed on the tops and the parts of the sides of the two conductive blocks. A second conductive line functioning as a word line is formed on the first dielectric layer, wherein the second conductive line has a part deposited between the two conductive blocks and is substantially perpendicular to the first conductive line and two doping region functioning as bit lines.

Memory structure and method of manufacturing a memory array

A flash memory includes: a plurality of switches; a global bit line; and a plurality of memory blocks, each containing a plurality of local bit lines, and a plurality of memory units coupled to the plurality of local bit lines respectively. A first switch couples a first local bit line to the global bit line; a second switch couples a second local bit line to the global bit line; a third switch couples the first local bit line to a first voltage source; and a fourth switch couples the second local bit line to a second voltage source.

Flash memory structure

A method for erasing data of a flash memory is disclosed. The flash memory includes a plurality of memory cells coupled to a word line, where each of the memory cells has a substrate, an isolated carrier storage layer, and a control gate coupled to the word line. And the method includes: coupling the substrate to a first voltage to increase a voltage level of the substrate; before erasing data, floating the control gate to make a voltage level of the control gate increase with the voltage level of the substrate; and coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer for erasing data.

Method for erasing flash memories and related system thereof

Triple well floating gate memory and operating method with isolated

Stacked read-only memory

An improved floating gate memory cell, having a dual thickness floating gate oxide, minimizes the band-to-band tunneling current and hot hole injection current suffered by the device, maximizes the Fowler-Nordheim tunneling current, allows lower operational voltages and provides a scalable structure. The process for manufacturing the dual thickness floating gate oxide structure comprises the steps of (1) forming a thicker insulator region over a channel region on the substrate, the thicker insulator having a source side and a drain side; (2) forming a thinner insulator on one or both of the source side and the drain side of the thicker insulator, and over a tunnel region in the substrate that is adjacent to the channel region; and (3) after forming the thinner insulator, distributing dopants in the source and the drain so that a concentration of dopants in the tunnel region beneath the thinner insulator is near or greater than a degenerately doped concentration. The step of distributing the dopants involves a process which does not damage the thinner insulator in the tunnel region. The floating gate is formed over the thicker insulator and the thinner insulator, and a control gate insulator and control gate are formed to complete the structure of the device. In this manner, a high-quality tunnel oxide is grown over the substrate while it is moderately doped. After growing a high quality tunnel oxide, the source and drain dopants are distributed into the device. In the tunnel region, where the floating gate oxide is thinner, the concentration of dopants in the substrate is quite high due to the source and drain dopants. This prevents band bending, at a level sufficient to induce band-to-band tunneling. In the channel region, where the concentration of dopants is more moderate, the thicker insulator prevents formation of an electric field sufficient to induce significant band-to-band tunneling.

Process for manufacturing a dual floating gate oxide flash memory cell

Growing community of inventors

Hsinchu, Taiwan

Fu-Chia Shone