Industrial Technology Research Institute

Fu-Cheng Tsai

Chih-Sheng Lin

Jian-Wei Su

Tuo-Hung Hou

Sih-Han Li

Yu-Hui Lin

Shih-Chieh Chang

Shyh-Shyuan Sheu

Heng-Yuan Lee

Kuo-Hua Tseng

Tay-Jyi Lin

Chih-Ming Lai

Yi-Ching Kuo

Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

Memory cell

An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Apparatus and method for neural network computation

A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

Data feature augmentation system and method for low-precision neural network

According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

Memory circuit with sense amplifier calibration mechanism

A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Computing in memory cell

A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.

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Tainan, Taiwan

Fu-Cheng Tsai