Murata Manufacturing Co., Ltd.

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Murata Integrated Passive Solutions

Ipdia

Frédéric Voiron

Julien El Sabahy

Guy Parat

Larry Buffle

Brigitte Soulier

Mohamed Mehdi Jatlaoui

Sami Oukassi

Stéphane Bouvier

Jean-René Tenailleau

Hiroshi Nakagawa

Sophie Archambault

Valentin Sallaz

Raphaël Salot

Naoki Iwaji

Paul-Henri Haumesser

Emmanuel Lefeuvre

Nicolas Normand

Pierre Noe

Maxime Lemenager

Yves Aubry

Sébastien Iochem

Ludovic Fourneaud

Sébastien Jacqueline

A semiconductor structure that includes a protruding wall structure that extends from a base surface of a substrate. Corners of the protruding wall structure may be smoothed or rounded to reduce electrical stress within the structure. The protruding wall structure may be partitioned into multiple wall regions disposed along different directions of the substrate to reduce mechanical stress.

Semiconductor structure enhanced for high voltage applications

A capacitor structure that includes a substrate; a conductive layer above the substrate; and a porous layer, above the conductive layer, having pores that extend perpendicularly from a top surface of the porous layer toward the conductive layer. The porous layer comprises a first region in which pores conductive wires are disposed, and a second region in which pores a metal-insulator-metal (MIM) structure is disposed. The first region may be used as a via to contact a bottom electrode of the capacitor structure.

Capacitor structure with via embedded in porous medium

A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.

Method of fabricating a semiconductor structure with improved dicing properties

An electrical device that includes: a metal barrier layer; an anodic porous oxide region on the metal barrier layer; a trench around the anodic porous oxide region reaching the metal barrier layer; a liner at least on a wall of the trench on a side of the anodic porous oxide region forming an electrical isolation barrier and having an opening onto the anodic porous oxide region; a hard mask arranged above the trenches and the liner having an opening onto the anodic porous oxide region. A corresponding manufacturing method is also disclosed.

Device having an anodic porous region surrounded by a trench having an electrical isolation barrier

An electronic component comprising a 3D capacitive structure includes a substrate having a contoured surface comprising a plurality of wells extending from the surface into the substrate body, a dielectric formed over, and conforming to the shape of, the contoured surface, and a first electrode formed over the dielectric and conforming to the contoured surface shape. The substrate constitutes a second electrode and the dielectric is interposed between it and the first electrode. Portions of the dielectric are exposed through openings at the base of the contoured surface and contact an insulating layer formed under the substrate, reducing the electrostatic field arising in the contacted portions of the dielectric when a potential difference is applied between the first and second electrodes. The openings at the bottom of the wells are obturated by the dielectric, defining blind holes within the wells, and the first electrode is in the blind holes.

Electronic component comprising a 3D capacitive structure

A current path is provided through an interposer to ground a grounding pattern associated with a transmission line, by exploiting an interposer substrate that has a high-resistivity portion at a first surface and a low-resistivity portion extending from the high-resistivity portion to a second surface of the interposer. Moreover, a set of blind via-holes comprising electrically-conductive material extend from the first surface of the interposer substrate through the high-resistivity portion and into the low-resistivity portion. Top-to-bottom connection can be made using the conductive material in the blind vias and using the low-resistivity portion of the substrate, while the high-resistivity portion of the substrate impedes current leakage from the transmission line to the second surface of the substrate. The number and dimensions of the blind via-holes control the impedance of the grounding pattern relative to the transmission line's characteristic impedance.

Through-interposer grounding using blind vias

An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.

Electrical device comprising a capacitor wherein the dielectric comprises anodic porous oxide, and the corresponding manufacturing method

A structure that includes: an insulating layer; a first metal layer above a first portion of the insulating layer; a first porous region of anodic oxide, above and in contact with the first metal layer; and a second porous region of anodic oxide, surrounding the first porous region, in contact with a second portion of the insulating layer adjacent to the first portion of the insulating layer, and in contact with the first metal layer, the second porous region forming an insulating region.

Method for forming product structure having porous regions and lateral encapsulation

A semi-conductor structure with a crack-blocking three-dimensional structure is described. The semiconductor structure includes a substrate; a functional circuit structure disposed in an area of the substrate; and a three-dimensional structure having at least one continuous trench that extends perpendicularly towards a base surface of the substrate and that surrounds the area of the substrate containing the functional circuit structure.

Semiconductor structure with crack-blocking three-dimensional structure

A nanowire structure is manufactured by forming islands of conductive material on a substrate, and a conductive sacrificial layer in the space between conductive islands. The conductive islands include an anodic etch barrier layer. An anodizable layer is formed, over the conductive islands and sacrificial layer, and anodized to form a porous template. Nanowires are formed in regions of the porous template that overlie the conductive islands. Removal of the porous template and sacrificial layer leaves a nanowire structure including isolated groups of nanowires connected to respective conductive islands which function as current collectors. Respective stacks of conductive and insulator layers are formed over different groups of the nanowires to form respective capacitors that are electrically isolated from one another. A monolithic component may thus be formed including an array of isolated capacitors formed over nanowires.

Manufacturing method of a nanowire-based structure and capacitor array component including the structure

A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

Semiconductor structure with selective bottom terminal contacting

A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

Trench capacitor structure with hybrid filling layer

A nanomagnetic inductor core that includes: a porous, electrically-insulating template having high-permeability material in the pores thereof to constitute elongated nanowires, and wherein the elongated nanowires are segmented along their axial direction; and a segment of dielectric material interposed between adjacent segments of the high-permeability material along the axial direction of the nanowire; wherein each segment of the high-permeability material has a length, in the axial direction of the nanowire, no greater than a size of a single magnetic domain, and wherein a maximal cross-sectional dimension of the nanowire is no greater than the size of the single magnetic domain. Inductors and LC interposers using such nanomagnetic inductor cores, as well as associated fabrication methods.

Nanomagnetic inductor cores, inductors and devices incorporating such cores, and associated manufacturing methods

A semiconductor device that includes a porous anodic region for embedding a structure. The porous anodic region is defined by a ductile hard mask. The ductility of the hard mask reduces the potential for the hard mask to crack during the formation by anodization of the porous anodic region. The ductile hard mask may be a metal. The metal may be selected to form a stable oxide when exposed to the anodization electrolyte thereby enabling the hard mask to self-repair if a crack occurs during the anodization process.

Semiconductor device having porous region embedded structure and method of manufacture thereof

Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.

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Barraux, France

Frédéric Voiron