Atmel Corporation

Nordic Semiconductor Asa

Frode Milch Pedersen

Sebastien Jouin

Stein Danielsen

Bartosz Gajda

Fredrik Larsen

Ian Fullerton

Laurentiu Birsan

Thierry Delalande

Sylvain Garnier

Ronan Barzic

Ivar Holand

Kristoffer Koch

Are Arseth

Martin Olsson

Thierry Gourbilleau

Arne Aas

Patrice Menard

Mickael Le Dily

Romain Oddoart

Marc Laurent

Andreas Engh Halstvedt

Francois Fosse

Jan Rune Herheim

Tor Erik Leistad

Cedric Favier

Kai Kristian Amundsen

James Hallman

Nicolas Graffet

Anthony Rouaux

Andreas Due Engh-Halstvedt

Ingar Hanssen

Erik Knutsen Renno

Stefan Markus Schabel

Morten Werner Lund

Samuli Hallikainen

Erwin Dotzauer

Jean-Baptiste Brelot

Xavier Leprevost

Joseph Martinez

Kai Renton

Oyvind Skutlaberg

Markku Vähätaini

Torbjørn Viem Ness

Mona Opsahl

Frederic Igier

Torbjorn Viem Ness

A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.

Processing apparatus

A circuit portion comprises a DCDC converter that provides current to one of a plurality of loads at a time. A controller detects when a voltage across an under-supplied load of the plurality of loads is below a first threshold. Channel logic circuitry provides current from the converter to the under-supplied load in response to the controller detecting that the voltage is below the first threshold. A voltage regulator provides current to the under-supplied load when the voltage is below a second threshold.

DCDC converters

According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (). The received address is mapped () to a slave address. Default access permissions are associated () to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (). The master-slave connection is enabled () if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.

Bus decoder

An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.

Management of power to internal subsystems within a system on chip

A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes. In an embodiment, a cryptographic accelerator comprises: an interface configured to receive cryptographic data, the cryptographic data indicating a particular cryptographic process to be performed on the cryptographic data; transformation logic configured to perform a cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic for performing cryptographic operations for a plurality of different cryptographic processes; and a state register configured for storing a result of the cryptographic operation.

Low cost cryptographic accelerator

A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Clock circuit portions

A clock selector circuit receives a first input clock signal (CLK) having a first frequency, and a second input clock signal (CLK) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK) and the second input clock signal (CLK), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK) or in the second input clock signal (CLK), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK) and the second input clock signal (CLK).

Clock selector circuit

An inter-process signaling system and method support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

Inter-process signaling system and method

In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

Memory emulation mechanism

The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.

Security extensions for non-volatile memory

Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is 'unlocked' the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is 'locked' the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Centralized peripheral access protection

A circuit includes a pulse generator coupled to a switch mode power supply. The switch mode power supply includes a switching component configured for transferring a charge to an energy storage component in response to pulses provided by the pulse generator. A pulse counter is coupled to the pulse generator or the switching component and configured to count pulses over a time period and thereby generate a pulse count. A converter coupled to the pulse counter is configured to generate a power measurement for the time period based on the pulse count. If the switch mode power supply has different modes of operation, a different counter may be used for each mode.

Instrumenting switch mode power supply to measure circuit power consumption

Systems, methods and computer-readable mediums are disclosed for providing secure access in a microcontroller system. In some implementations, a microcontroller system comprises a system bus and a secure central processing unit (CPU) coupled to the system bus. The secure CPU is configured to provide secure access to the system bus. A non-secure CPU is also coupled to the system bus and is configured to provide non-secure access to the system bus. A non-secure memory is coupled to the system bus and is configured to allow the secure CPU and the non-secure CPU to exchange data and communicate with each other. A peripheral access controller (PAC) is coupled to the system bus and configured to enable secure access to a peripheral by the secure CPU while disabling non-secure access to the peripheral based upon a non-secure state of the non-secure CPU.

Secure access in a microcontroller system

Growing community of inventors

Trondheim, Norway

Frode Milch Pedersen