Intrinsity, Inc.

Apple Inc.

Fritz A Boehm

James S Blomgren

Jean Anne Booth

Terence M Potter

Shawn D Strawbridge

Douglas N Good

Laura A Weber

Jeffrey S Leonard

Ben D Jarrett

Laura A Potter

Edmond R Bures

Terri Lynn Fukuhara

Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.

Hardware state data logger for silicon debug

An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.

Automatically identifying resettable flops for digital designs

A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations.

Automated functional coverage for an integrated circuit design

A method is contemplated in which the stimulus to an IC design simulation may be automatically manipulated or steered so that the test environment is altered during subsequent simulations of the IC design based upon the simulation results and/or configuration settings of previous simulations of the IC design. More particularly, a stimulation steering tool may analyze the simulation results and/or the test environment, and manipulate the test environment, which may include the test generator output, and the test bench model, for subsequent simulations.

Automated stimulus steering during simulation of an integrated circuit design

A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a simulation stimulus on a test bench and saving the simulation output. The reference IC design corresponds to an IC design model having visibility to comprehensive internal device state. The method may also include simulating a modified version of the reference IC design using the same simulation stimulus on the same test bench, and saving the modified version simulation output. In addition, the simulation outputs of the reference IC design and the modified version are compared to create a comparison result. Lastly, the method may include determining whether the modified version of the reference IC design is functionally equivalent to the reference IC design based upon the comparison result.

Method for verifying functional equivalence between a reference IC design and a modified version of the reference IC design

A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, if an event is detected on a speed path, the endpoint of that speed path may be forced to a failing value, and the simulation may be resumed. At some point later in the simulation, the simulation results may be checked to determine if a failure that corresponds to the failing value was observed at a structure that would be visible on a manufactured version of the IC design. If the failure is visible, the test vectors that were used may be identified and captured for use in production testing.

Identifying speed binning test vectors during simulation of an integrated circuit design

The monitor manager manages the execution of monitors during the simulation of a digital design. The monitor manager () includes an instance generator () that creates executable instances () of monitors that may be time-dependent monitors, an activation manager () that assigns instances to be active or inactive, and an execution unit () that executes active instances and receives returned status values passed, failed, active, or error. Executable instances of time-dependent monitors are software state machines having a state variable, one or more time-dependent variables, and at least two state-driven code blocks, at least one of which might be either a cycle-dependent code block that tests for a specific cycle-dependent condition, or an event-dependent code block that tests for a specific event-dependent condition. In either case, the state-driven code block increments the time-dependent variable, and, when the condition has been satisfied, increments the state variable.

Monitor manager that creates and executes state machine-based monitor instances in a digital simulation

An expansion syntax that creates a set of expressions in software code is disclosed. The syntax includes one or more expansion constructs embedded within a software code expression, interpreted by an expansion function to create a set of expanded expressions. Each construct includes an expansion syntax indicator and a plurality of list parameters, which may be start, end, step, and skip integers, or strings of non-white space. Both constructs may include either default or expressly assigned list names, which serve as iterators during the expansion process. Each expanded expression created includes a list member from each embedded construct. The expansion methodology, and the resulting set of expanded expressions, depends upon the number of unique iterators present in the software code expression and whether any of the embedded constructs include the stride parameter.

Expansion syntax

The disclosed invention is a grid that monitors a design simulation to support design verification coverage analysis. The disclosed invention includes n ordered axis declarationsthat each correspond to a functional attribute and list at least two valid functional states, logic expressionsthat test for the functional states and set axis variables, and a grid declarationthat converts the axis variables to a unique linear index value corresponding to the cross-product of the achieved functional states and records hits. The linear index is calculated by multiplying the integer value of each axis variable (except the nth axis variable) by the product of the sizes of each higher-order axis than the axis to which said axis variable corresponds, summing the results, and adding the integer value of the nth said axis variable.

Grid that tracks the occurrence of a N-dimensional matrix of combinatorial events in a simulation using a linear index

A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Software modeling of logic signals capable of holding more than two values

The present invention is a monitor that detects a design verification event and reports a status event to a database. One embodiment of the present invention comprises a monitor declaration, zero or more signal declarations, zero or more bus declarations and one or more logic expressions. A logic expression, formulated using the declared signals and buses, is used to evaluate whether a specific verification event has occurred. The present invention further comprises a monitor where the signal of the signal declaration of the monitor is an N-Nary signal. Additionally, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.

Method and apparatus for a monitor that detects and reports a status event to a database

A random number indexing method and apparatus includes an index array that uniquely identifies each pseudo-random number in a sequence of numbers generated by a pseudo-random number generator . A computer program provides a seed value to the pseudo-random number generator and populates the index array. The computer program uses the identifying indicia in the index array to call for and receive pseudo-random numbers.

Random number indexing method and apparatus that eliminates software call sequence dependency

A static output signal is generated using a static storage element ( ) and transmitted to a NDL gate ( ) over a transmission path ( ) that is characterized by a user-specified multi-cycle timing constraint that is used to create appropriate verification tests of the apparatus. The multi-cycle timing constraint may be a pragma that is interpreted by the compiler of a timing analysis tool such as PATHMILL to automatically check the set-up and hold times of the static signal relative to the rising edge or falling edge of user-specified clock signal pulses. The same pragma is interpreted by the compiler of a functional verification tools such as VIS to create statements that test the behavior of the apparatus during the clock signal pulses other than the user-specified clock signal pulses tested by the timing analysis tool.

Static transmission of FAST14 logic 1-of-N signals

Multiple-state simulation for non-binary logic

The present invention is a grid that is a monitor that detects a cross product of design verification events and reports a single status event to a database. One embodiment of the present invention comprises axes declarations, logic expressions, and a grid declaration. An axes declaration produces a cross product of verification events. A logic expressions evaluates whether a specific verification event has occurred. A grid declaration returns the status event. The present invention further comprises a grid where the cross-product of verification events comprises a fully or a sparsely populated cross-product of verification events. Additionally, the present invention further comprises a grid that uses N-Nary signals. And, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.

Growing community of inventors

Dripping Springs, TX, United States of America

Fritz A Boehm