Itt Industries, Inc.

Deutsche Itt Industries Gmbh

Friedrich Schmidtpott

Laurin C Freyberger

Reiner Backes

Daniel Mlynek

Peter M Flamm

Dieter Holzmann

Wolfgang Sauer

Mathew Neal

Alfred Praxmarer

Hermanus Schat

The burst signal existing on the back porch of the composite color signal is brought to a predetermined normalized value with the aid of an amplitude control loop. In order to further increase the gain of a multiplier provided for in the control loop the multiplier is preceded by a premultiplier of simple design, whose multiplication factor is capable of being switched over in powers of two. A multiplication factor setting signal, is converted via a code converter into two control signals, with the first control signal setting the multiplication factor of the premultiplier, and with the second control signal setting the multiplication factor of the multiplier.

Integrated digital gain control circuit for digital chrominance signals

A circuit is described which holds the bootstrap node of a MOS push-pull end stage at a constant potential even if the end stage has to generate an output H-level. A diode/capacitor charge pump circuit supplies the required pulse current only fed to the node in case of the output H-level.

MOS bootstrap push-pull stage

In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white-level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.

Set of three integrated circuits for digital video signal processing in

Digital color signal processing circuitry includes a multiplier which multiplies two demodulated digital color-difference signals by a digital color-saturation signal to provide three time-division-multiplexed signal pairs, each of which is added to the digital luminance signal by an adder. The color-saturation-signal input of the multiplier is preceded by a second multiplier to which the color-saturation signal and multiplier factors stored in a memory (sp) are applied. These multiplier factors are permanently stored by the manufacture of the color-television receiver or can be varied or adjusted during the operation of the receiver. The three adders are followed by three digital-to-analog converters which provide the analog color signals.

Digital signal processing circuitry for a color-television receiver

An improved digital integrated chrominance-channel circuit having gain control for color-television receivers includes at least one integrated circuit for digitally processing the composite color signal. The circuit includes a first limiter inserted between a parallel multiplier and a burst-amplitude-measuring stage, and a control stage including a parallel subtracter whose minuend input is fed with a reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage. A digital accumulator whose enable input is presented with a signal derived from the trailing edge of a burst gating signal is used as an integrator.

Digital integrated chrominance-channel circuit with gain control

An improved kit of two integrated circuits having a phase-locked loop clock oscillator for use in a color television receiver utilizing digital signal processing is described. The voltage controlled oscillator and the phase discriminator of the phase-locked loop are each located in a different one of the two integrated circuits. The control signals for the voltage controlled oscillator are transferred into it via a two-wire digital bus. External discrete components are eliminated.

Integrated circuit kit with a phase-locked loop for color television

In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.

A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) connected in series with respect to the signal flow. The complex gate (KG) consists of two NORed AND elements (U1, U2). The output of the second inverter (I2) is the count-up output (VA), and that of the third inverter (I3) is the count-down output (RA). The count-up output (VA) is coupled through a second transfer transistor (T3), controlled by the second clock signal (F2), to the first input of the first AND element (U1), whose second input is connected to the output of the first inverter (I1). The count-down output (RA) is coupled through a third transfer transistor (T2), controlled by the second clock signal (F2), to the first input of the second AND element (U2), whose second input is connected to the output of the NOR gate (NG) through a fourth transfer transistor (T 5), which is also controlled by the second clock signal (F2). One of the two inputs of the NOR gate is connected to the carry input (UE) in each stage. The carry input (UE) is connected to the carry output (UA) of the stage through a carry transfer transistor (UT). The carry input (UE) of the least significant stage is grounded. The second input of the NOR gate (NG) is connected to a stop line (S). The carry output (UA) is connected to a constant voltage (U) through a transfer transistor (T4) controlled by the countdown output (RA). In a second variant, the complex gate (KG) is omitted, so that the output of the first inverter (I1') is connected directly to the input of the second inverter (I2') through the first transfer transistor (T1'). The output of the NOR gate (NG') controls the gate of the second transfer transistor (T2'). Its first input is fed with the first clock signal (F1'), and its second input is connected to the carry input (UE). Those ends of the current paths of the second and third transfer transistors (T2', T3') not connected to the outputs are coupled to the input of the inverter (I1').

Dynamic synchronous binary counter with stages of identical design

The monolithic integrated binary MOS parallel comparator uses enhancement-mode insulated-gate field effect transistors of the same conductivity type and comprises n successively weighted stages each including a NOR block having at least two inputs each receiving a correspondingly weighted digit of a different one of a first and a second n-digit binary word and an additional logic circuit also receiving the correspondingly weighted digit of the first and second words, and an output logic circuit coupled to each of the n stages to provide an output signal for the comparator.

Binary MOS parallel comparators

A binary-to-decimal code converter consists of matrix-like arranged MOS transistors connected in series and parallel to each other in order to enable the optimum space arrangement on the chip.

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Gundelfingen, Germany

Friedrich Schmidtpott