Koninklijke Philips Corporation N.V.

Mentor Graphics Corporation

Nxp B.v.

Friedrich Hapke

Michael Wittke

Andreas Glowatz

Juergen Schloeffel

Reinhard Meier

Rene Krenz-Baath

Thomas Hans Rinderknecht

Hendrikus Petrus Elisabeth Vranken

Ruediger Solbach

Wilfried Redemund

Sascha Ochsenknecht

Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.

Cell-aware fault model generation for delay faults

Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.

Multi-targeting boolean satisfiability-based test pattern generation

On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with predefined waveforms during a capture period of a logic test, based on a clock control signal. The clock control signal may be supplied via a JTAG control port or via a scan chain load port. The clock control signal may also be generated by a BIST controller. The techniques may ensure glitch-free transitions from slow speed clocks during a shift period to fast speed clocks during a capture period.

High speed clock control

On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.

On-chip logic to log failures during production testing and enable debugging for failure diagnosis

An integrated circuit (IC) is disclosed that comprises a circuit portion () having a plurality of inputs () and a plurality of outputs (), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (), comprising a test pattern generator () for generating the test pattern, masking logic () for masking selected outputs of the plurality of outputs () and a signal generator () coupled to the masking logic () for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator () being responsive to clock cycle selection data (s-s). This way, selected clock cycles or individual flip-flops can be masked out without requiring external control signals. The IC may also comprise a mask storage arrangement () for storing masks to mask a plurality of scan chains for all cycles within a pattern.

Testable integrated circuit and test data generation method

Techniques for storing and using compressed restrict values for selected scan chains and flip-flops, such that the states that need to be applied to those flip flops need not be solved by a linear equation system solver, such as a linear equation system solver provided by an automatic test pattern generation (ATPG) tool. Selected restrict values can then be injected into test patterns for those flip-flop combinations that need to be set in a certain shift cycle or those flip-flops that need to be initialized one after another (e.g., for serial settings in one scan chain).

Deterministic logic built-in self-test stimuli generation

Techniques are provided for X-masking using at least some masking information provided by on-chip logic, in lieu of masking information provided from off of the integrated circuit being tested. The masking information is provided by a masking information source on the integrated circuit being tested, such as, for example, a read-only memory (ROM) circuit, that feeds the masking information to the X-masking logic. With these implementations of the invention, it is possible to perform X-masking independent from any external data, thus enabling X-masking for a logic built-in self-test without requiring an external testing device.

On-chip logic to support compressed X-masking for BIST

According to an example embodiment, there is an integrated circuit arrangement with at least one application circuit to be tested, and with at least one self-test circuit for testing the application circuit and generating at least one pseudo-random test sample. wherein said The pseudo-random test sample is converted into at least one test vector that is programmable and/or deterministic and is supplied to the application circuit for testing purposes via at least one logic gate and at least one signal that is applied to said logic gate. The output signal arising in dependence on the deterministic test vector is evaluated by the application circuit by at least one signature register. Furthermore, there is a method of testing the application circuit such that Built In Self Test (BIST) hardware connected to the additional deterministic logic is reduced; it is suggested that the signal supplied to the logic gate is made available by a Bit Flipping Function (BFF) logic circuit based on at least one self-test circuit.

Circuit arrangement and method of testing an application circuit provided in said circuit arrangement

An apparatus for testing an integrated circuit is disclosed. The apparatus includes a compactor to compress test responses from a circuit under test that is part of an integrated circuit.

Method and system for selectively masking test responses

In an arrangement for testing an integrated circuit comprising a combinational logic system, which arrangement performs a test of the behavior of the combinational logic system in comparison with test software which emulates the nominal behavior of the integrated circuit, the signal edge behavior of the combination logic system is checked in that that the test software comprises two identical software models of the combinational logic system to be tested, in which a test sample is applied for test purposes to a first of these software models and whose output signals are coupled to a second of these software models, in that the integrated circuit comprises a test circuit which, in a test mode, applies a first test sample in a first test clock cycle to the input of the combinational logic system of the integrated circuit and takes over the output signal in a buffer memory and which feeds back this output signal as a second test sample in a second test clock cycle to the input of the combinational logic system and again takes over the output signal of the combinational logic system in the buffer memory, and in that at the end of the second test clock cycle, the arrangement compares the results of the combinational logic system of the integrated circuit in the buffer memory with the results of the second software model.

Arrangement and method of testing an integrated circuit

Integrated circuit with an application circuit () to be tested, and a self-test circuit (-) which is provided for testing the application circuit () and comprises an arrangement (-) for generating desired test patterns which are applied to the application circuit () for test purposes, wherein the output signals occurring in dependence upon the test patterns through the application circuit () are evaluated by means of a signature register (), the arrangement (-) for generating the desired test patterns comprising a bit modification circuit () which individually controls first control inputs of combination logics () in such a way that a pseudo-random sequence of test patterns supplied by a shift register is modified such that, by approximation, the desired test patterns are obtained, and which controls second control inputs of the combination logics (), by means of which the first control inputs can be blocked, such that those test patterns that are supplied by the shift register () and are already desired test patterns are not modified by the bit modification circuit () by means of controlling the first control inputs of the combination logics ().

Integrated circuit with test circuit

An integrated circuit () with an application circuit () to be tested and a self-testing circuit (-), which is provided for testing the application circuit () and generates pseudorandom test patterns, which can be transformed, by means of first logic gates () and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit () for testing purposes, wherein the output signals occurring through the application circuit () as a function of the test patterns are evaluated by means of a signature register (), wherein, by means of second logic gates () and signals fed to said gates, those bits of the output signals of the application circuit () which, due to the circuit structure of application circuit (), have undefined states, are blocked during testing.

Integrated circuit with self-testing circuit

In an arrangement for testing an integrated circuit comprising at least two circuit sections ( ) which in normal operation operate with at least two different clock signals, a minimal number of test runs for testing the integrated circuit is required because the integrated circuit to be tested is formed in such a way that each clock signal can be individually switched on and off during a test by test software provided in the arrangement, a software model of the circuit to be tested is provided in the arrangement, which software model comprises an X generator ( ) for those circuit components ( ) whose mode of operation is influenced by a plurality of clock signals and their skew behavior, which X generator is activated and supplies an X signal when more than one clock signal influencing the mode of operation of the circuit components ( ) during testing is activated, while, during testing, the test software initially activates all clock signals and evaluates test results for those circuit components ( ) for which no X signal appears in the software model ( ), and because for those circuit components ( ) for which an X signal appeared in the software model ( ) during testing with all clock signals, the test software performs a plurality of test runs in which each time only one or more of the clock signals influencing the mode of operation of the circuit component ( ) is/are activated and evaluates only those tests of the circuit components ( ) of the circuit for which no X signal appears in the software model ( ).

In an integrated circuit comprising an application circuit ( ) to be tested and a self-test circuit ( - ) which is provided for testing the application circuit ( ) and comprises an arrangement ( - ) for generating deterministic test samples which are applied to the application circuit ( ) for test purposes, the output signals occurring due to the application circuit ( ) in dependence upon the test samples being evaluated by means of a signature register ( ), an unlimited ON-chip testing possibility of the integrated circuit without additional circuit elements in the application circuit ( ) is ensured for test purposes in that the self-test circuit ( - ) comprises a masking logic element ( ) which, during testing, blocks those bits of the output signals of the application circuit ( ) which, based on the circuit structure of the application circuit ( ), have undefined states and applies only the other bits to the signature register ( ).

Integrated circuit with self-test circuit

The invention relates to an arrangement for testing an integrated circuit ( ). In order in this case to avoid a test vector memory and an on-board test system, a data word generator ( ), which supplies deterministic data words, means ( ) for test pattern generation, which modify the deterministic data words such that prescribed test patterns are produced which can be fed to inputs of an integrated circuit ( ) to be tested, and comparison means ( ) for comparing test output patterns of the integrated circuit ( ) with desired output patterns.

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Winsen, Germany

Friedrich Hapke