Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Oregon State University

Freeman Yingquan Zhong

Lizhi Zhong

Yi Zeng

Yikui (Jen) Dong

Amaresh Virupanagouda Malipatil

Yikui Jen Dong

Cathy Ye Liu

Ye Liu

Peter John Windler

Steven L Howard

Chintan M Desai

David S Lowrie

Mohammad Shafiul Mobin

Chaitanya Palusa

Weiwei Mao

Jeffrey A Hall

Hiroshi Kimura

Wing Liu

Patrick Yin Chiang

George C Tang

Eric M Zhang

Tai Jing

Wenyi Jin

Ryan Jungsuk Park

Wingfaat Liu

Tao Jiang

Hollis H Poche, Jr

Venkata Naga Jyothi Madhavapeddy

Shao Ming Hsu

Cathy Ye Lin

Catherine Chow

Eric W Zhang

In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

SerDes PVT detection and closed loop adaptation

An apparatus having a circuit is disclosed. The circuit may be configured to (i) receive an input signal from a communication channel and (ii) generate an intermediate signal by amplifying the input signal (a) by a low-frequency gain in response to an amplitude control signal and (b) by a high-frequency gain in response to a boost control signal.

Extended variable gain amplification bandwidth with high-frequency boost

A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link. The hybrid receiver equalizer can also be used in receivers for simultaneous forward and back-channel transmission using differential-signaling in multi-Gbps transceivers.

Band-pass high-order analog filter backed hybrid receiver equalization

A method and system of adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE) are disclosed. In one embodiment, a method of adjusting a setting of a linear equalizer includes determining a change to a decision feedback equalizer (DFE) tap weight value of a predefined metric according to a data signal and an error signal (e.g., the change may be generated according to an average of a specified plurality of data signals and the error signal); using the change in the DFE tap weight value to algorithmically generate a modification in a linear equalizer setting; and adjusting the linear equalizer setting. The linear equalizer is located in a feed-forward path and/or a feedback path of data transmission. The linear equalizer may be located in a transmitter and/or a receiver. The linear equalizer may be a continuous time linear equalizer and/or a Finite Impulse Response (FIR) linear equalizer.

Adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE)

In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.

Adjusting sampling phase in a baud-rate CDR using timing skew

Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.

Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage

A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.

Time-interleaved track-and-hold circuit using distributed global sine-wave clock

An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

Floating-tap decision feedback equalizer for communication channels with severe reflection

Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Data latch circuit and method of a low power decision feedback equalization (DFE) system

In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL.

PVT consistent PLL incorporating multiple LCVCOs

A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.

Hybrid bump capacitor

A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

Solution for package crosstalk minimization

An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

Re-adaption of equalizer parameter to center a sample point in a baud-rate clock and data recovery receiver

In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.

AC coupling circuit integrated with receiver with hybrid stable common-mode voltage generation and baseline wander compensation

The present invention is a self-calibrating, dual-band, wide range LC tank Voltage Controlled Oscillator (VCO) system. The system may include a first Voltage-Controlled Oscillator (VCO) and a second Voltage-Controlled Oscillator (VCO). The system may further include a calibration engine. The calibration engine may be configured for being connectable to at least one of the first VCO or the second VCO. The calibration engine may further be configured for automatically establishing/providing a VCO fix capacitor band code setting and a gear control setting for selectively activating or inactivating the first VCO and/or the second VCO. The calibration engine may be further configured for automatically comparing a VCO control voltage of the system to an allowable control voltage range for the system and may be further configured for automatically adjusting the VCO fix capacitor band code setting and/or the gear control setting when the VCO control voltage falls outside of the allowable control voltage range.

Growing community of inventors

San Ramon, CA, United States of America

Freeman Yingquan Zhong