Applied Materials, Inc.

Fredrick Fishburn

Gill Yong Lee

Sung-Kwan Kang

Chang Seok Kang

Nitin K Ingle

Sony Varghese

Tomohiko Kitajima

Arvind A Kumar

Christopher Sean Olsen

Qian Fu

Nicolas L Breil

Zhijun Chen

Takehito Koshizawa

Hansel Lo

Byeong Chan Lee

Hao Zhang

Abdul Wahab Mohammed

Raghuveer Satya Makala

Hoi-Sung Chung

Kristopher Mikael Koskela

A method for forming an oxide layer includes forming a protective interlayer oxide on sidewalls of a trench formed on a substrate, forming a silicon nitride layer on the protective interlayer oxide, by a plasma-enhanced atomic layer deposition (PE ALD) process utilizing nitrogen-containing process gas, the silicon nitride layer having a concentration gradient of nitrogen varying from high concentration away from the protective interlayer oxide to low concentration near the protective interlayer oxide, and performing a conversion process to oxidize the formed silicon nitride layer to at least partially convert the formed silicon nitride layer to a silicon oxide layer.

Growth of thin oxide layer with silicon nitride and conversion

Methods of forming a three-dimensional dynamic random-access memory (3D DRAM) structure are provided herein. In some embodiments, a method of forming a 3D DRAM structure includes forming at least one wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises: vertically etching a first pattern of holes; filling the first pattern of holes with a silicon germanium fill; vertically etching a plurality of isolation slots through the first stack; filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill; etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and depositing a layer of conductive material that wraps around the plurality of gate silicon channels.

Three-dimensional dynamic random-access memory (3D DRAM) gate all-around (GAA) design using stacked Si/SiGe

The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.

System and methods for dram contact formation

Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate, planarizing the substrate to the CMP stop layer, removing a portion of a top of the two Si walls and forming an L-pad formation, deep etching a pattern of holes into the space between the two Si walls in horizontal portions of the plurality of alternating Si layers and SiGe layers, and forming vertical wordline structures from the pattern of holes in the horizontal portions.

Methods and apparatus for hierarchical bitline for three-dimensional dynamic random-access memory

Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Selection gate separation for 3D NAND

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

Replacement channel process for three-dimensional dynamic random access memory

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Three-dimensional dynamic random access memory (DRAM) and methods of forming the same

Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.

Method to scale dram with self aligned bit line process

Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

Growing community of inventors

Aptos, CA, United States of America

Fredrick Fishburn