U.S. Philips Corporation

Digital Equipment Corporation

Frederik Zandveld

Matthias Wendt

Marnix Claudius Vlot

Marcel D Janssens

Jacobus M Bakker

Peter Klapproth

Gerardus C Van Loo

Peter C Van Der Vliet

Hendrik A Klap

Daniel Schouten

Jeroen M Visser

Jose A De Oliveira

J A Kindervater

Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are being read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

Processor architecture with independently addressable memory banks for storing instructions to be executed

A data processor, includes a central processing unit, an interrupt handler for selectingly signalling a single interrupt vector to the central processing unit, and multiple interrupt sources that are daisy-chained to the interrupt handler, for therewith exchanging interrupt request signals and interrupt acknowledge signals. A Bus (or buses) interconnects all above subsystems. The interrupt handler communicates a read vector command to all interrupt sources in parallel and thereupon allows transmitting an actual interrupt address vector on the bus.

Solid state data processor with versatile multisource interrupt

Microprocessor with registered clock counting for at a predetermined count producing a command signal of adjustable shape, and a hierarchical interrupt system for use therewith. A microprocessor comprises registered counting means that counts clock pulses. Upon attainment of a predetermined count it generates a command signal. Furthermore, it has a presettable input section that recurrently receives a variable preset count for downcounting, a secondary count section that is fed by said command signal output for counting successive command signals and under control of attainment of a predetermined count generates a secondary command signal on a secondary output. Next, a programmable registered pulse shaper mechanism under control of said secondary command signal executes serial shifting and outputs a shaped version of the secondary command signal. The above counting means is also associated to a parametrizeable interrupt priority mechanism.

Signal generating device including programmable counters and a

A computer system includes a single-chip central processor (20) with handshaking and direct memory access (DMA) controllers for accommodating first and second types of DMA to a dynamic random access memory (DRAM) (34). The single-chip central processor (20) has a kernel processor (22) having cache, a memory management and control unit (26), and a coprocessor (24). The computer system further includes a bundle of lines (28), including data lines, address lines and row address strobe (RAS), column address strobe (CAS), output enable (OE), and write enable (WE) lines for coupling the memory management and control unit (26) to the DRAM (34), and a plurality of data exchanges (33, 37) coupled to a plurality of first and second attach controllers (32, 36). The coprocessor includes a plurality of DMA controllers (240-246) for storing addresses and for storing a length representing a number of data items to be transferred. Additionally, each DMA controller is coupled by a separate line (303) to a respective first attach controller for accommodating a first type of DMA, between the memory and the plurality of data exchanges, which generates addresses of contiguous memory. The plurality of second attach controllers accommodates a second type of DMA between the memory and the plurality of data exchanges. The coprocessor further includes a plurality of handshake controllers (250-256), each for executing handshaking with a respective second attach controller, not under control of the kernel processor.

Sparc RISC based computer system including a single chip processor with

A microprocessor includes a processor element, a memory interface element, an IO interface element, a debug support element and an internal bus interconnecting all above elements. For easy debugging, it also includes attached to the internal bus a registered boundary scan standard (JTAG) interface that accesses one or more scan chains inside the microprocessor, and is arranged for controlling DMA-type exchanges via the internal bus with other elements connected to this bus.

Microcontroller provided with hardware for supporting debugging as based

A processor in a computer system is connected, together with one or more control units of peripheral apparatus, to the main memory via a main bus. For a very fast processor the storage capacity of the main memory should be so high that the full physical address can no longer be transported via the main bus in one operation. In that case an additional communication line is provided between the processor and the main memory. In order to enable peripheral apparatus to access the entire main memory anyway, a second memory management unit is connected between the main bus and the main memory.

Computer system comprising a main bus and an additional communication

A computer system having a central machine, work stations and a background memory, wherein the central machine has an active state, a standby state, a battery power supply state and a rest state, a heart memory maintains the actual time and contains information indicating at what time of what days the active state should prevail. When the mains power supply fails the central machine goes over to the battery power supply state. When the latter is failing, the battery indicator is set in an 'error' state. When the mains power supply reappears, it is inspected whether then the active state has to be maintained and under the control of an 'error' position an initial program load operation is carried out. If admissible the central machine goes over to the standby state.

Computer system with work stations at remote positions and reserve

A computer system comprises a bus for data, address and control signals which is divided into a left bus and a right bus by a first gating device. The gating device has an open state which is character-wise activated by a right bus request transported on the left bus. Furthermore, the gating device conducts start signals from a processor station connected to the left bus and interrupt signals from a peripheral apparatus connected to the right bus. In the closed state of the gating device, bulk data transport is possible on the right bus without interfering with the processor station. The processing speed is thus increased.

Computer system comprising a data, address and control signal bus which

In a data processing system a control device for an intermediate memory during a bulk data transport between two data devices. A first data device addresses a number of descriptor signals. Each descriptor signal indicates another descriptor signal, so that a sequence is formed which is cyclically coupled end-around. The descriptor signals indicate either a memory section or a branch to a remote address in the memory. The memory sections used may thus be distributed throughout the memory. Additional descriptor signals indicate, in a direct or indirect manner, a descriptor signal of the sequence for each of the two data devices. A handshake by way of signal bits is present at the level of the memory sections.

Growing community of inventors

Eindhoven, Netherlands

Frederik Zandveld