Bell Telephone Laboratories

At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Frederick Vratny

Hyman J Levinstein

William T Lynch

Eliezer Kinsbron

King Lien Tai

David B Fraser

John M Andrews, Jr

Martin E Poulsen

Alfred Zacharias

A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.

Fabrication of FETs with source and drain contacts aligned with the gate

A unique socket assembly is designed to interconnect a flat-pack-packaged integrated-circuit chip to a printed-circuit board in a manner that permits easy insertion and withdrawal of the packaged chip from the assembly. A base portion of the assembly includes a recess into which conductive cantilevered elements extend. When the packaged chip is positioned on these elements within the recess and a lid is placed on the base, secure but not permanent electrical contact is established between the elements and contact regions on the chip package.

Connecting a flat-pack-packaged chip to a printed circuit board

A method and apparatus for fabricating a device is disclosed, which method involves a new reactive ion etching technique. Both a high etch rate and, for example, a high etch selectivity are simultaneously achieved with the inventive reactive ion etching technique by discharging an electrode of the reactive ion etching apparatus in response to a preselected criterion, e.g., a magnitude of a DC bias at said electrode which equals, or exceeds, a preselected value.

Method for fabricating devices with DC bias-controlled reactive ion

A polyarylate polymer is deposited on a substrate in accordance with a fabrication procedure that ensures an adherent low-stress conformal coating. Such a coating is advantageous for use in a number of industrial applications of practical importance.

Polyarylate polymer coatings

A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate.

Fabrication of FETs

It has been discovered that the diffusion of hydrogen species into the outside or water-cooled surface of a pure palladium anode included in an X-ray source causes various deleterious effects. To avoid these effects, a limited-depth hydrogen-barrier layer made, for example, of Pd.sub.3 Sn is formed within the anode extending from the outside surface thereof. The inside or target surface and a major extent of the palladium anode remain virtually unaffected during the forming step. The desired palladium emission characteristic of the anode is thereby preserved. In practice, the modified anode remains free of hydrogen and, as a result, exhibits a particularly advantageous long-life property. Such an anode constitutes an important part of a high-power X-ray lithographic system adapted for making VLSI devices.

X-Ray source and method of making same

In a plasma-assisted etching apparatus and method designed to pattern silicon dioxide in a plasma derived from a mixture of trifluoromethane and ammonia, surfaces in the reaction chamber are coated with a layer of silicon. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Apparatus and method for plasma-assisted etching of wafers

In a plasma-assisted etching apparatus and method designed to pattern aluminum or polysilicon, surfaces in the reaction chamber are coated with a layer of aluminum oxide. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.

Method of fabricating high-conductivity silicide-on-polysilicon

In an integrated circuit fabrication sequence, a hardened mask pattern adhered to an underlying substrate is removed from the substrate by a solvent that comprises anhydrous hydrazine and dimethyl sulfoxide. The solvent rapidly penetrates the interface between the pattern and the underlying substrate and quickly breaks the adhesive bonds therebetween. Other materials (e.g., Al, Si, SiO.sub.2) in the structure being fabricated are not deleteriously affected by the solvent.

Removing hardened organic materials during fabrication of integrated

A fabrication process for making palladium-plated target anodes for X-ray lithographic systems is characterized by a unique sequence of surface preparation, plating and annealing steps. Anodes made by the process have been operated reliably at high-power levels for extended periods of time.

Fabrication of palladium anode for X-ray lithography

Even ultra-thin films deposited on the surface of a high-power X-ray target anode (14) during water cooling thereof form thermal barriers that significantly limit the lifetime of the anode. The deposition of such films on the anode is minimized by utilizing several techniques. These include the use of low-corrosion metals such as high-chrome stainless steel in the cooling system, preferential etching of the water-carrying metallic members to provide chrome-rich surfaces, and complexing the metallic hydroxides that are produced in the cooling medium to hold them in a highly soluble state even in the immediate vicinity of the hot anode. These techniques, coupled with submicron filtering and systematic cleaning and maintenance of the cooling system, are important contributors to achieving highly reliable long-lifetime operation of a high-power X-ray source.

High-power X-ray source

A method for depositing electroless nickel on aluminum or aluminum alloy is described. The method is particularly useful for fabricating bonding pads on aluminum metallized semiconductor devices and for creating beam leads. The described method deposits a thick nickel layer directly on aluminum without the use of intermediate layers or surface activation as required in the prior art. The method basically comprises immersion in a stop-etchant which simultaneously removes aluminum oxide and activates the surface; immersion in a solution which activates the aluminum with nickel ions and deactivates mask material; and immersion in a novel electroless nickel bath. A technique for electrolessly depositing gold is also described.

Growing community of inventors

Berkeley Heights, NJ, United States of America

Frederick Vratny