International Business Machines Corporation

Frederick T Blount

Daniel Francis Casper

Robert S Capowski

Arnold Weinberger

Terrence K Zimmerman

Lawrence R DelSonno

Robert F Geller

Joseph M Kusmiss

An (M plus K)-digit accessed address is checked to see if it may fall within a range of addresses g defined by the address at one end of the range plus a variable range of addresses (g). The checking is done in a single step in a comparison of the K lowest order address digits for both addresses. The K digits of the two addresses are checked against one another in two separate segments, a pointer segment and a range segment. The pointer segments of the two addresses are examined to see if any one of three relationships which would possibly place the accessed address within the range exists. The range segments of the two addresses are examined at the same time for an additional requirement to place the accessed address in the range.

Address range determination

A channel communicator CC has a storage array for holding an entry for each channel and for holding a busy vector and an interrupt vector that each have a bit for each channel. The CC is connected between the input bus and the output bus that connect the channels and an I/O processor IOP to processor main store. A message to the CC includes the ID of the channel that the message is to or from and the CC uses this ID as an address for accessing a channel entry or a bit in a vector. The message also carries a command that controls the CC to store a data portion of a message or to fetch a channel entry or a vector from the array and load it onto the output bus addressed to the IOP or to one of the channels. The command also controls addressing a particular one of the vectors. The CC also has means responsive to a command to perform a sequence of operations for testing the vectors and for testing fields of an entry in the array and for using the results of the test to control the execution of the command.

Channel communicator

The range of output binary numbers from a number substitution mechanism receiving input binary numbers, and which include first and second storage arrays addressed by first and second of the input binary number is substantially reduced by interleaving alternate output signals from the storage arrays which have been provided selectable binary numbers in certain storage locations accessed by certain ones of the input binary numbers. Further, compression of the range of output of binary numbers as substitution for certain ones of the binary input binary number is achieved by addressing the first and second storage arrays by first and second portions of the input binary number to which a certain number of the input signal line of the first and second portions are common.

Binary number substitution mechanism

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Hopewell Junction, NY, United States of America

Frederick T Blount