Juniper Networks, Inc.

Intel Corporation

Raza Microelectronics, Inc.

Nvidia Corporation

Netlogic Microsystems, Inc

Rmi Corporation

Frederick R Gruner

Nazar A Zaidi

Ramesh Panwar

Elango Ganesan

Robert G Hathaway

David T Hass

Mark Vilas

Mark Bryers

Michael Freed

Abbas Rashid

Ricardo Ramirez

Yen C Lee

Sankar Ramanoorthi

John Phillips

Yuhong Zhou

Gregory G Spurrier

Chau Anh Ngoc Nguyen

Puneet Agarwal

Gaurav Singh

Brian Hang Wai Yang

Sophia W Kao

Ralph Portillo

Shirish C Gadre

Kushagra V Vaid

Ashish Karandikar

Franciscus W Sijstermans

Bharat N Zaveri

Christopher M Eccles

Samir C Vora

Chau Ahn Ngoc Nguyen

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Content service aggregation system

A method for context switching on a video processor having a scalar execution unit and a vector execution unit. The method includes executing a first task and a second task on a vector execution unit. The first task in the second task can be from different respective contexts. The first task and the second task are each allocated to the vector execution unit from a scalar execution unit. The first task and the second task each comprise a plurality of work packages. In response to a switch notification, a work package boundary of the first task is designated. A context switch from the first task to the second task is then executed on the work package boundary.

Context switching on a video processor having a scalar execution unit and a vector execution unit

A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.

Prefix matching structure and method for fast packet switching

A precedence determination system including a first type memory bank configured to receive a first search signal and to provide first search result indications, a second type memory bank configured to receive a second search signal and to provide second search result indications, a precedence number table coupled to the first and second type memory banks and configured to provide programmable precedence numbers, and a precedence determination circuit coupled to the first and second type memory banks and the precedence number table and configured to provide a third search result indication is disclosed. In one embodiment, the first type memory bank can be a static random access memory (SRAM) and the second type memory bank can be a ternary content addressable memory (TCAM).

Method and apparatus for determining precedence in a classification engine

A configurable lookup table extension system including a plurality of lookup tables arranged in an internal memory, an external memory, and a flexible controller configured to couple at least one of the plurality of lookup tables to the external memory through a single memory interface is disclosed. Implementations of this system can support the flexible allocation of IP and MAC table entries so that a router/switch can flexibly support applications suited to a particular allocation. This approach provides an efficient scheme for extending multiple internal tables to external memory via a single external interface. Further, such extensibility is also programable to allow the size and number of external tables to be configured by software. This solution can provide the flexibility of customizing table sizes for different markets and/or customer requirements.

Method and apparatus for providing internal table extensibility with external interface

A compute engine allocates data path bandwidth among different classes of packets. The compute engine identifies a packet's class and determines whether to transmit the packet based on the class' available bandwidth. If the class has available bandwidth, the compute engine grants the packet access to the data path. Otherwise, the compute engine only grants the packet access to the data path if none of the other packets waiting for data path access have a class with available bandwidth. After a packet is provided to the data path, the compute engine decrements a bandwidth allocation count for the packet's class. Once the bandwidth count for each class is exhausted, the compute engine sets each count to a respective starting value&#x2014;reflecting the amount of bandwidth available to a class relative to the other classes. A compute engine employing the above-described bandwidth allocation can be employed to perform different networking services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Bandwidth allocation for a data path

A compute engine's central processing unit is coupled to a coprocessor that includes application engines. The central processing unit initializes the coprocessor to perform an application, and the coprocessor initializes an application engine to perform the application. The application engine responds by carrying out the application. In performing some applications, the application engine accesses cache memory&#x2014;obtaining a physical memory address that corresponds to a virtual address and providing the physical address to the cache memory. In some instances, the coprocessor employs multiple application engines to carry out an application. In one implementation, the application engines facilitate different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Application processing employing a coprocessor

A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a media access controller engine and a data transfer engine. The media access controller engine couples the compute engine to a communications network. The data transfer engine couples the media access controller engine to a set of cache memory. In further embodiments, a compute engine includes two media access controller engines. A reception media access controller engine receives data from the communications network. A transmission media access controller engine transmits data to the communications network. The compute engine also includes two data transfer engines. A streaming output engine stores network data from the reception media access controller engine in cache memory. A streaming input engine transfers data from cache memory to the transmission media access controller engine. In one implementation, the compute engine performs different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Co-processor including a media access controller

A system includes a plurality of processing clusters and a snoop controller adapted to service memory requests. The snoop controller and each processing cluster are coupled to a snoop ring. A first processing cluster forwards a memory request to the snoop controller for access to a memory location. In response to the memory request, the snoop controller places a snoop request on the snoop ring&#x2014;calling for a change in ownership of the requested memory location. A second processing cluster receives the snoop request on the snoop ring. The second processing cluster generates a response to the snoop request. If the second processing cluster owns the requested memory location, the second processing cluster modifies ownership status of the requested memory location.

Ring-based memory requests in a shared memory multi-processor

A multi-processor unit includes a set of processing clusters. Each processing cluster is coupled to a data ring and a snoop ring. The unit also includes a snoop controller adapted to process memory requests from each processing cluster. The data ring enables clusters to exchange requested information. The snoop ring is coupled to the snoop controller&#x2014;enabling the snoop controller to forward each cluster's memory requests to the other clusters in the form of snoop requests.

Ring based multi-processing system

A system for processing data includes a first set of cache memory and a second set of cache memory that are each coupled to a main memory. A compute engine coupled to the first set of cache memory transfers data from a communications medium into the first set of cache memory. The system transfers the data from the first set of cache memory to the second set of cache memory, in response to a request for the data from a compute engine coupled to the second set of cache memory. Data is transferred between the sets of cache memory without accessing main memory, regardless of whether the data has been modified. The data is also transferred directly between sets of cache memory when the data is exclusively owned by a set of cache memory or shared by sets of cache memory. In one implementation, the above-described cache memory arrangement is employed with a compute engine that provides different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Processing packets in cache memory

Growing community of inventors

Palo Alto, CA, United States of America

Frederick R Gruner