International Business Machines Corporation

Frederick O Flusche

Benedicto U Messina

James R Robinson

Bruce L McGilvray

Ethel L Richardson

Kwang G Tan

Richard N Gustafson

Joseph A Wetzel

Charles W Evans

Ralph W Wright

Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS). Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage. In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands. After any line conflict is found for any other cache in the MP, the completion of the CL command is delayed by cancelling the line pad write request to MS. Then the IE repeatedly reissues the CL command until all found conflicting lines are invalidated. As soon as no conflict is found in any copy directory, the currently issued CL command is completed by not cancelling the pad data request to MS, so that pad bytes are then written into the line in MS.

Store-in-cache processor means for clearing main storage

A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD). Each PD has a plurality of line entries which define the content of corresponding line positions in the associated SIC. Each line entry has an associated data shareability control bit, designated EX, which may be set to a one or zero state to indicate, respectively, the exclusive (EX) or readonly (RO) state of the associated line. An exclusive line is not shareable, but a readonly line is shareable i.e. may exist validly in more than one SIC in the MP. Any CP in the MP can request data in an EX state from its SIC, which data may or may not be found in its SIC or in another CP's SIC. If a CP requests a line of storage data in EX state and the line is found in EX state in another CP's SIC, it may be allowed to remain in the other CP's SIC by being set to RO state in both CPU SICs for the situations in which: (1) the line is found unchanged in EX state in the other CP's SIC, or (2) the line is found in RO state in the other CP's SIC, in which case the line is received and set to RO state in the requesting SIC even though requested in EX state. But if the line is found to be changed in the other CP's SIC, its shareability designation in the requesting SIC will be EX and the line is invalidated in the other CP's SIC from where it is castout.

Cache storage line shareability control for a multiprocessor system

The disclosure provides a storage protection (SP) array in each of two system controllers (SCs) in a multiprocessing system which has a shared main storage containing a plurality of basic storage modules (BSMs). The BSMs may be operated with block and page interleaved addresses. Each block in main storage is assigned a key-in-storage having an entry in one of the two arrays. A cross-interrogate (XI) bus connects between the SCs. Using the XI bus, each processor request is sent to an SP address register in every SP array. Each array is divided into a plurality of equal groups. Each group has a range identifier register and a comparator. The range identifier register is loaded with a value which controls the range of main storage addresses to which the group is assigned. All of the comparators in each array are connected to a high-order part of the SP address register for the array. The range identifier registers in all of the groups in both arrays are assigned different values which cover the entire address range of main storage, and only one array need contain a particular key-in-storage. A BSM bit and a page bit in the processor request address are put into the high-order field of the SP address register to control the selection of a group, so that alternate pages have their keys-in-storage put in different groups in a pair of groups in a SP array. Key-in-storage accesses may be overlapped between different groups in an array. When a request received from the XI bus has its key-in-storage found in one array, the key-in-storage is transmitted on the XI bus to the SC which sent the request.

Reconfigurable key-in-storage means for protecting interleaved main

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Hyde Park, NY, United States of America

Frederick O Flusche