Sk Hynix Memory Solutions Inc.

Skhynix Inc.

Dell Products Inc.

Frederick K H Lee

Jason Bellorado

Lingqi Zeng

Xiangyu Tang

Arunkumar Subramanian

Marcus Marrow

Zheng Wu

Robert J Proulx

Girish B Desai

Ameen Aslam

Zhenwei Wang

Christopher S Tsang

Yuanzheng Cai

Fan Zhang

Naveen Kumar

Seungjune Jeon

Johnny A Lam

Leland W Thompson

Stephen J Silva

Matthew Lewis Call

Michael Rijo

Samuel Hudson

Justin L Ha

Hsiao-Heng Lee

Yunhsiang Hsueh

Jie Wu

Shwetashree Virajamangala

Nagabhushan Hegde

A storage device syndrome-weight-based error correction system includes a syndrome-weight-based error correction subsystem that is coupled to a storage subsystem in a chassis. The syndrome-weight-based error correction subsystem performs a first error correction hard decoding operation on the storage subsystem that utilizes first read voltage thresholds and that generates a first final codeword candidate having a first syndrome weight. The syndrome-weight-based error correction subsystem then performs error correction hard decoding read voltage threshold real-time search operations to determine second read voltage thresholds, and performs a second error correction hard decoding operation on the storage subsystem that utilizes the second read voltage thresholds and that generates a second final codeword candidate having a second syndrome weight. If the syndrome-weight-based error correction subsystem determines that the first syndrome weight is less than the second syndrome weight, it performs error correction soft decoding operations using the first read voltage thresholds.

Storage device syndrome-weight-based error correction system

A storage device syndrome-weight-based error correction system includes a syndrome-weight-based error correction subsystem coupled to a storage subsystem in a chassis. The syndrome-weight-based error correction subsystem performs a plurality of respective first error correction hard decoding operations on the storage subsystem that each utilize respective read voltage thresholds and that each generate a respective final codeword candidate having a respective syndrome weight. The syndrome-weight-based error correction subsystem identifies a first syndrome weight of a first final codeword candidate that was generated via the performance of one of the plurality of respective first error correction hard decoding operations that utilized first read voltage thresholds and that is lower than the syndrome weights of the final codeword candidates generated via the performance of the others of the plurality of respective first error correction hard decoding operations, and performs error correction soft decoding operations using the first read voltage thresholds.

A storage operation suspend system includes a chassis having a storage operation suspend subsystem coupled to a communication system and a storage subsystem in the chassis. The storage operation suspend subsystem performs a first storage operation on a storage die in the storage subsystem, receives a second storage operation instruction via the communication system to perform a second storage operation on the storage die, determines that the second storage operation is a higher priority operation than the first storage operation, determines that a first power amount available in a power budget and a second power amount allocated from the power budget to the first storage operation is sufficient to perform the second storage operation when the first storage operation is suspended and, in response, suspends the first storage operation and performs the second storage operation and, following completion of the second storage operation, resumes performance of the first storage operation.

Storage operation suspend system

A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.

Storage subsystem read voltage determination system

A storage device RAID data write intermediate parity system includes a storage device coupled to a host system and including a storage subsystem and a volatile memory system. The storage device RAID data write intermediate parity system receives first primary data from the host system, and stores the first primary data in the volatile memory system. The storage device RAID data write intermediate parity system then stores a first subset of the first primary data in the storage system, generates first intermediate parity data using the first subset of the first primary data, stores the first intermediate parity data in the volatile memory system and, in response, erases the first subset of the first primary data from the volatile memory system.

Storage device raid data write intermediate parity system

In general, embodiments of the invention relate tracking the operating temperature of the solid-state memory modules (SSMMs) in order to improve their performance.

Temperature-adjusted power-on data retention time tracking for solid state drives

A system for controlling a solid state drive is disclosed that includes a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks. A pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices. An effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device.

Method for estimating data retention time in a solid state drive

Window based mapping is used to reduce the usage of volatile memory for storing the mapping of logical to physical addresses for accesses to data in a flash drive. Two separate mapping tables for translation of logical addresses to physical addresses (L2P), e.g., an L2P front map and an L2P back map, are used where the L2P front map acts as a window to the L2P back map. The L2P front map has smaller granularity for data accesses than the L2P back map. The data accessed using the L2P front map can allow the flash drive to function with relatively same performance as a fully mapped drive with a single mapping table.

Window based mapping

Memory systems may include a memory including a plurality of blocks, and a controller suitable for determining a pool of blocks from the plurality of blocks as garbage collection (GC) victim block candidates based on a number of valid pages left in each of the plurality of blocks, and selecting a block from the pool of blocks having a minimum number of valid pages as a victim block for garbage collection.

Data separation by delaying hot block garbage collection

A plurality of bins and a plurality of soft read values are stored in a lookup table where those bins that are either a leftmost bin or a rightmost bin correspond to soft read values having a maximum magnitude. Bin identification information is received for a cell in solid state storage. A soft read value is generated for the cell in solid state storage, including by: accessing the lookup table, mapping the received bin identification information to one of the plurality of bins in the lookup table, and selecting the soft read value in the lookup table that corresponds to the bin which is mapped to.

Generating soft read values which optimize dynamic range

A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.

Reading and writing to NAND flash memories using charge constrained codes

A total bytes written (TBW) requirement associated with solid state storage is obtained. A size of a cache associated with the solid state storage is determined based at least in part on the TBW requirement. The size of the cache is adjusted to be the determined size

Sizing a cache while taking into account a total bytes written requirement

Methods may include after a power loss, determining a most recently saved section of a logical block addressing (LBA) table, a previous section saved prior to the most recently saved section of the LBA table, and a least recently saved section of the LBA table, reading an open super block and updating entries in the LBA table from the most recently saved section through to the least recently saved section, reading a newest closed super block from a plurality of closed super blocks and updating entries in the LBA table from the previous section saved prior to the most recently saved section through to the least recently saved section, and reading an oldest super block and updating entries in the LBA table in the least recently saved section.

Memory system and operating method for improving rebuild efficiency

Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

Delaying hot block garbage collection with adaptation

Methods of encoding a near-symbol balanced (NSB) sequence may include selecting, with a controller, a constraint based on an amount of bits, determining, with the controller, a plurality of sections in a codebook based on permutations defined by the selected constraint, and partitioning, with the controller, a section among the plurality of sections into a plurality of partitions until each of the plurality of partitions include a number of entries equal to or less than a predetermined number of entries.

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Mountain View, CA, United States of America

Frederick K H Lee