Intel Corporation

Frederick J Pollack

Konrad K Lai

Glenn J Hinton

Andrew F Glew

David B Papworth

Robert P Colwell

Robert S Dreyer

Daniel G Lau

Tsu-Hua Wang

William M Corwin

Shreekant S Thakkar

Stephen Anthony Fischer

James A Valerio

Michael A Fetterman

Donald B Alpert

David A Cobbley

Ronald J Ebersole

Robert R Sullivan

Michael Alan Fetterman

Jack L Klebanoff

Robert H Childs, Jr

A software method of setting a state in a processor regarding whether a processor number encoded in the processor will be available for reading is described. The method comprises prompting the user to enter an indication whether the processor number should be available for reading by a program. Then, setting a state to inhibit the processor number from being read by a program if the indication indicates that the processor number should not be available for reading by the program. For one embodiment, the method further includes testing the indication if a request for the processor number is received, and releasing the processor number if the indication indicates that the processor number is available.

Processor unique processor number feature with a user controllable disable capability

A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Apparatus and method for identifying the features and the origin of a

A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

Methods and apparatus for determining operating characteristics of a

A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

Methods and apparatus for determining memory operating characteristics

A computer arrangement that offloads computationally intensive tasks from portable computer devices to larger servers is disclosed. A portable computer device that relies on handwriting or speech for input is equipped with a wireless communication subsystem. When a user writes on the display or speaks into the portable computer device, the central processing unit passes the handwriting or speech information to the wireless communication subsystem. While the user is still inputting information, the wireless communication subsystem transmits received information to a communication server. The communication server routes the handwriting or speech information to a server that performs handwriting or speech recognition to translate the information into encoded text. The communication server then transmits the encoded text information back to the portable computer device.

System for processing handwriting written by user of portable computer

A subsystem call mechanism for communicating between a first execution environment associated with a first domain object, and a second execution environment associated with a second domain object. An environment table object is associated with a process object. The environment table object includes a control stack which is an array of control stack entries which entries save the state of the first calling execution environment to be restored on a return from the second execution environment. A subsystem entry in the subsystem table specifies the object that defines region 2 of the target execution environment and the frame pointer of the topmost stack frame in the target environment, a supervisor Stack Pointer that is a linear address for the supervisor stack used when involving a supervisor call in the user mode (instead of the stack pointer in the current frame) to locate the new frame. The first domain object further includes Procedure Entries that specify the type and address of the target procedure. Each of the procedure entries includes a Procedure Entry Type field that indicates the type of procedure to be invoked, either a supervisor procedure or a subsystem procedure, and an offset into the target execution environment. The offset specifies the first instruction of the target procedure.

Synchronous communication between execution environments in a data

An object-oriented computer architecture in which access descriptors include an object index for selecting an object in the address space, and a rights field specifying the permissible operations on a bi-paged object selected by the access descriptor. A local object lifetime bit is provided in the encoded fields portion of access descriptors, object descriptors, and page table entries to determine the lifetime of an object. The AD lifetime bit in the encoded fields of AD is compared in OTE Lifetime Check Logic with the destination object lifetime, the OTE local bit in the encoded fields of the OTE access descriptor. The OTE local bit in the encoded fields of the OTE is compared in PDTE Lifetime Check Logic with the destination object lifetime, the PDTE local bit in the encoded fields of the PDTE access descriptor. The PDTE local bit in the encoded fields of the PDTE is compared in PTE Lifetime Check Logic with the destination object lifetime, the PTE local bit in the encoded fields of the PTE access descriptor. If any of these checks fails, a protection lifetime fault is asserted.

Object lifetime control in an object-oriented memory protection mechanism

Access descriptors (24) include an object index (34) for selecting an object in the address space, and a rights field (35) specifying the permissible operations on a bi-paged object (38) selected by the access descriptor. An object table (42) has stored therein object descriptors for use in forming physical addresses to the page table directory object (60) which has page table descriptors stored therein for accessing page tables. A page table (44) has stored therein page table entries for use in forming physical addresses to the paged object (38). Logic compares the page rights field (81) of the page table entry with the rights field (62) of the page table descriptor in the page table directory entry and asserts a fault if the access permitted by the page rights field (50) is inconsistent with the rights field of the access descriptor in the page table directory entry. A mechanism provides for the implicit deallocation of certain objects and to prevent dangling references if access descriptors which point to objects with shorter lifetimes are stored in objects with longer lifetimes. Special Instructions provide a mechanism for the amplification or restriction of the rights of access descriptors.

Type management and control in an object oriented memory protection

A star local area network includes a ring bus hub (4) capable of being connected to a plurality of nodes (3, 5, 9) geographically distant from the hub by means of low speed serial links (18, 19, 21, 28). The nodes include processor means (2, 30, 31) for creating messages for transfer on the network. A plurality of duplex communication links (18, 19, 21, 28) connect the nodes to the ring bus hub (4). The hub (40) is comprised of a plurality of ring controllers (10, 12, 14, 16) driven by a common clock source (7). Each ring controller is connected by means of a number of parallel lines to other ring controllers in series to form a closed ring. Each one (3) of the plurality of nodes is geographically distant from the hub (4) and is connected to a corresponding one (10) of the ring controllers by means of one (18, 19) of the duplex communication links. The node controllers including node interface means (40) for transmitting the messages as a contiguous stream of words on the duplex communication link. The ring controllers include ring bus interface means (42) for forming the messages into discrete data packets for insertion onto the ring bus and means (32, 34) for bufferring data messages received form the node and over the ring bus.

Local area network with an active star topology comprising ring

A memory management and protection mechanism in which access to protected entitites is controlled. The protected entities are represented by descriptors. Each protected entity is accessed via a selector which comprises an index integer assigned to the descriptor at the time of its creation. Tasks are active entities which may perform accesses and therefore are subject to control. A task has certain access rights. Each protected entity is assigned a specific privilege level. Each task within the system operates at one and only one privilege level at any instant in time. Protected entities which reside at a privilege level which is equal or less privileged than the current privilege level (CPL) of the task are generally accessible. The effective privilege level (EPL) of an access to a protected entity is defined as the numeric maximum of the CPL and the requested privilege level (RPL) present in the selector pointing to the memory segment to be accessed. An access is permitted if and only if the EPL is numerically less than or equal to the descriptor privilege level (DPL), assigned to the protected entity.

Growing community of inventors

Portland, OR, United States of America

Frederick J Pollack