General Electric Company

Burr-brown Corporation

Texas Instruments Corporation

Monolith Technologies Corporation

Frederick J Highton

Jimmy R Naylor

Stephen Robert Wynn

Ronald F Cormier

Arvid E Englund, Jr

Robert L White

Earnest A Franke

Kun Lin

Gary L Miller

Christopher Paul Lash

Rodney A Dolman

Akhtar Ali

David S Trager

Rickey D Harris

Kazuo Ito

A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational amplifier having first and second inputs coupled to first and second input sampling capacitors, respectively, and first and second feedback capacitors coupled between the first and second inputs and first and second outputs of the operational amplifier. A continuous-time offset DAC receives a digital input signal representative of an offset voltage produces first and second offset correction voltages. The first and second offset correction voltages are coupled to the switched-capacitor sample/hold circuit to adjust the amount of pre-charging of the first and second feedback capacitors, respectively, in accordance with the value of the digital input signal to compensate an offset component associated with the and second input voltages. The output of the switched-capacitor sample/hold circuit can be connected to an ADC.

Switched capacitor circuit with current source offset DAC and method

A digital signal processor (DSP) circuit is configured to recursively retrieve and process pairs of data points in a symmetric digital filter. The data points are retrieved from an external source (e.g., compact disk) at a first frequency, and processed within the DSP at a second frequency. The DSP employs a floating pointer scheme, which effectively functions a buffer to thereby compensate for jitter or drift between the first and second frequencies.

Digital-to-analog converter including integral digital audio filter

A CMOS digital-to-analog converter includes a modified R-2R resistive ladder network connected to 16 pairs of bit switches responsive to the various digital inputs to produce an internal analog voltage representative of the digital input. Each pair of bit switches includes an N-channel MOSFET and a P-channel MOSFET. The on resistance of the P-channel MOSFET is adjusted to precisely match that of the N-channel MOSFET by driving the gate of each P-channel MOSFET with the output of a CMOS inverter referenced between V.sub.CC and a reference voltage that is adjusted to cause the on resistances of a P-channel 'monitor' MOSFET and an N-channel 'monitor' MOSFET to be equal. A reference voltage is generated by a circuit that generates a temperature-invariant source current from a V.sub.BE difference between first and second transistors, causes part of it to flow through first, second, and third resistors, the third resistor having a voltage across it established by the V.sub.BE voltage of a transistor and having a predetermined negative temperature coefficient, the second and third resistors being composed of nichrome, the first resistor being lightly doped P-type material the resistance of which has a positive temperature coefficient.

CMOS digital-to-analog converter circuitry

A serial-to-parallel converter receiving a clock signal and continuous serial stream of input data, each having TTL logic levels, produces parallel outputs for driving current switches of a digital-to-analog converter (DAC). The data and clock signals each are converted to ECL logic levels by a pair of emitter-coupled differential lateral PNP transistors having their collectors coupled to a pair of NPN current mirror circuits, the outputs of which drive the bases and emitters of a pair of NPN emitter follower transistors, resulting in very high bandwidth operation. Master-slave ECL shift register bit outputs are directly coupled, without emitter followers, to ECL inputs of output latches that drive the DAC current switches, resulting in substantially reduced power consumption and chip area. Saturation of the emitter-coupled NPN transistors of the latch circuit is avoided by providing an upper supply voltage level for the load resistors of the master-slave shift register bits that is one diode drop lower than the upper supply voltage level for the load resistors of the latch circuit. A unique ECL one-shot circuit responds to an external latch enable control signal having TTL logic levels to produce internal complementary ECL enable signals that enable the output latches.

Level shifting circuitry for serial-to-parallel converter

A novel circuit architecture is disclosed for achieving audio, tone, and digital data signal modulation in a full duplex radio transceiver. A single signal source is utilized to generate both transmitted carrier and receiver local oscillator injection signals. Yet the architecture is such that the transmitted data does not appear at the receiver's discriminator output--while a 'side tone' of transmitted audio does so appear. The audio to be transmitted is used to frequency modulate a VCO and provide the receiver first mixer injection signal as well as a 'carrier' input to a phase modulator. The data/tone signals are on the other hand, combined and integrated in a complex waveform and input to control the phase modulator. The resulting FM (data/tone and voice) output from the phase modulator is then input to a conventional duplexed r.f. transmitter.

Duplex radio transceiver having improved data/tone and audio modulation

A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes a circuit for external adjustment of the bit current of a particular bit of the digital-to-analog converter, which circuit produces a constant adjustment current that is summed with that bit current over a wide range of processing parameters and temperature, and requires only a single terminal for connection of an external potentiometer by means of which the bit current is adjusted and a small value filter capacitor for filtering out noise generated by an internal zener diode voltage reference circuit.

Bit adjustment and filter circuit for digital-to-analog converter

An amplifier exploits Miller-effect capacitance in a cascaded multi-stage self-limiting amplifier arrangement to achieve automatic adaptive bandwidth behavior (without the use of an active feedback control loop). The Miller-effect capacitance varies in accordance with the amplifier signal-level, with the capacitance in turn varying the amplifier bandwidth. Bandwidth is decreased for low-signal-levels and increased for relatively high-signal-levels. The adaptive amplifier technique is especially useful to reduce broadband noise in an IF stage of a communications device before the usable signal is fed to a detector stage.

Adaptive bandwidth amplifier

Temperature compensation for received signal strength indications (RSSI) is provided by a reference circuit having the same temperature characteristic as the RSSI circuit, and by a difference circuit. The RSSI signal and the reference signal are applied to the difference circuit which provides a temperature compensated RSSI output in which temperature variations have been removed by the reference signal.

Received signal strength indicator

A radio transceiver has a single reference oscillator and a receiving frequency synthesizer and a transmitting frequency synthesizer. The synthesizer frequencies are selected so that the receiving intermediate frequency and a transmitting intermediate frequency (produced by the transmitted frequency mixing with the received frequency) are spaced widely apart. Thus, any beat note between the two intermediate frequencies is outside the passband or filter bandwidth in the receiver circuit.

Growing community of inventors

Tucson, AZ, United States of America

Frederick J Highton