International Business Machines Corporation

Globalfoundries Inc.

Other

Frederick Gustav Anderson

Robert Mark Rassel

Michael Joseph Zierak

Richard A Phelps

Natalie Barbara Feilchenfeld

Nicholas Theodore Schmidt

Yun Shi

David S Collins

David L Harmon

Zhong-Xiang He

Theodore James Letavic

Randy Lee Wolf

Yves T Ngu

Jenifer E Lary

Xudong Wang

Mark E Stidham

Jiansheng Xu

Michael Lawrence Gautsch

Philippe Ramos

Jean-Marc Petillat

The present invention relates to a container of storing packets of edible items. The container comprises a plurality of compartments for storing one kind of packet in each compartment, the compartments having an opening configured thereon; a lid having a handle, the lid being configured to selectively facilitate a ejection of at least one packet when the handle is operated by a user; and a biasing means configured at an operative bottom edge of the plurality of compartments, the biasing means configured to provide an upward push to the packets, thereby facilitating the ejection of the packets from the opening when the handle is operated by the user.

Container for storing and dispensing packets of edible items

A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.

Modeling localized temperature changes on an integrated circuit chip using thermal potential theory

Disclosed are embodiments for modeling integrated circuit (IC) performance. In these embodiments, a parasitic extraction process is performed to generate a netlist that, not only accounts for various parasitics within the IC, but also accounts for substrate-generated signal distortions (e.g., substrate-generated harmonic signal distortions) that occur within the IC. During this netlist extraction process, the design layout of the IC is analyzed to identify parasitics that are to be represented in the netlist and to also identify any circuit elements with output signals that are subject to substrate-generated signal distortions. When such circuit elements are identified, signal distortion models, which were previously empirically determined and stored in a model library, which correspond to the identified circuit elements, and which account for the signal distortions, are selected from the model library and incorporated into the netlist. Simulations are subsequently performed using this netlist to generate a performance model for the IC.

Integrated circuit performance modeling that includes substrate-generated signal distortions

Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (T) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (V) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance

Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (V) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vof the diode (e.g., increasing the length reduces Vof the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode

Isolated Zener diode

A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.

Schottky barrier diode with perimeter capacitance well junction

A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

Asymmetric junction field effect transistor

Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

Differential junction varactor

A system, apparatus and method for alignment of a marine engine in a water vessel with either an existing or a design propeller shaft line of a propeller shaft of the vessel. The invention is also useful in positioning and aligning propeller shaft supports to the design shaft line before being secured to the hull of the vessel under construction. A laser gun for projecting a laser beam, a plurality of laser targets positionable into the propeller shaft support members, and a unique laser beam splitter temporarily connected to the engine output shaft cooperate to provide opposing colinear laser output beams viewably emitting from the laser beam splitter only when the marine engine is properly oriented coaxially of the engine crankshaft centerline with respect to the shaft line.

Growing community of inventors

South Burlington, VT, United States of America

Frederick Gustav Anderson