Morgan/weiss Technologies Inc.

Triquint Semiconductor Corporation

Keyssa, Inc.

Analog Devices,inc.

Other

Tektronix, Inc.

Frederick George Weiss

Morgan T Johnson

Gary Davis McCormack

Ian A Kyles

Roger Dwain Isaac

Christopher Scott Sansom

Bhupendra Sarhad

Daniel G Knierim

Linda K Bebernes

Jim Y Li

Gary Davis Mccormack

A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between the peripheral circuit and the main processor, wherein the at least two interposer substrates are stacked such that the at least two peripheral circuits on each interposer substrate are stacked with the at least two peripheral circuits on another of the at least two interposer substrates.

Stacked and folded above motherboard interposer

An apparatus includes a processor having an array of processor interconnects arranged to connect the processor to conductive paths, a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects, an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate, and at least one peripheral circuit connected to the at least one conductive trace.

Interposer with high bandwidth connections between a central processor and memory

A test fixture has a flexible plastic cable that acts as a waveguide. The Device-Under-Test (DUT) is a small transceiver and antenna that operate in the Extremely High-Frequency (EHF) band of 30-300 GHz. The size of the DUT transceiver is very small, limiting the power of emitted electromagnetic radiation so that close-proximity communication is used. The envelope for reception may only extend for about a centimeter from the DUT transceiver, about the same size as the test socket. A slot is formed in the test socket very near to the antenna. The slot receives one end of the plastic waveguide. The slot extends into the envelope by the DUT transceiver so that close-proximity radiation is captured by the plastic waveguide. The waveguide has a high relative permittivity and reflective metalized walls so that the radiation may be carried to a receiver that is outside the envelope.

Waveguides for capturing close-proximity electromagnetic radiation transmitted by wireless chips during testing on automated test equipment (ATE)

A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace.

Above motherboard interposer with quarter wavelength electrical paths

A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, and peripheral circuit modules residing on the interposer substrate, wherein each peripheral circuit module has an electrical path having a path length to the main processor less than one-quarter of a wavelength of signals that will travel the electrical path.

A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.

Motherboard substrate having no memory interconnects

An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Above motherboard interposer with peripheral circuits

An ESD protection circuit utilizes a trigger network to allow the user to select the breakdown voltage of an avalanche transistor. By implementing the trigger network as a string of diodes coupled between the collector and base of the avalanche transistor, the trigger voltage can be programmed between BV and BV by adjusting the number of diodes. When the voltage across the trigger network reaches a predetermined value at which the diodes are conducting under forward biased conditions, but the transistor is below BV , base charge supplied to the transistor caused the transistor to avalanche. A base-emitter resistor prevents false triggering by removing leakage charge from the base of the transistor, and another resistor coupled in series with the base of the transistor limits the removal of charge, thereby causing the avalanche to be self-sustaining once initiated by the trigger network. One or more forward-biased diodes can be coupled in series with the transistor to increase the voltage across the protection circuit during avalanche. In an alternative embodiment, one or more diodes are connected in series with an open-base avalanche transistor for increasing the voltage across the protection circuit when the transistor avalanches, thereby increasing the margin between the avalanche voltage and the normal operating voltage.

ESD protection circuit with controlled breakdown voltage

Both differential and single-ended band-switchable VCOs are described. The single-ended version of the voltage controlled oscillator in its most basic form includes a load, two transistors, two delay elements, and a switchable current source. The first transistor includes a collector, an emitter and a base coupled to the load to form an output terminal for providing an oscillator output signal. The first delay element is connected between the collector and the base of the first transistor. The second transistor includes a collector, an emitter and a base connected to the base of the first transistor. The second delay element is connected between the collector of the first transistor and the collector of the second transistor. The switchable current source is connected to the emitters of the first and second transistors to provided a current to one of the transistors responsive to a control signal wherein the oscillator output signal has a first frequency of oscillation that is inversely proportional to the delay of the first transistor when the first transistor is turned on and a second frequency of oscillation inversely proportional to the sum of the first and second delay element delays when the second transistor is turned on.

Band-switchable, low-noise voltage controlled oscillator (VCO) for use

An electrical circuit (30) corrects for the presence of noise current and current drift in the currents developed by each current source transistor Q.sub.0, Q.sub.1, Q.sub.2, Q.sub.3, . . . Q.sub.n in a current source array. The electrical circuit corrects for the presence of noise current and current drift by simultaneously inducing in each current source correction currents whose values sum to cancel the current drift and noise. A noise suppression circuit includes an amplifier having an open loop gain, A.sub.v, which is configured to adjust the magnitudes of the multiple currents in response to the introduction of a noise current, i.sub..delta., in any one of the currents. The adjustment substantially cancels i.sub..delta. and thereby substantially reduces the presence of i.sub..delta. in the output current. The presence of i.sub..delta. in the output signal is substantially equal to i.sub..delta. /(1+A.sub.v).

Low noise DAC current source topology

A DAC includes a simple width-scaled weighted array (104) of N number of current sources and a weighted cascode current divider (108) comprised of m number of current sources. The simple width-scaled weighted array conducts N first scaled currents (I.sub.0 -I.sub.3), the array including N first transistors (116a-116d) connected to different ones of N second transistors (112a-112d), one of the N second transistors (112d) having a gate width w. The weighted cascode current divider includes M current sources, the current divider including M third transistors (120a-120d) that conduct M second scaled currents (I.sub.4 -I.sub.7) which are summed at a node (134). The node is connected to a master current transistor (138) that conducts a current I.sub.S and has a gate width w. In one embodiment, the bias of the N first transistors is tied to the node, whereby relative magnitudes of the N first scaled currents remain in correct proportion to relative magnitudes of the M second scaled currents in spite of changes in the magnitude of current I.sub.S. In another embodiment, the first and second inputs to an operational amplifier are connected to the node and the drain of the transistor of the second N transistors having a gate width w, respectively. The output to the operational amplifier is connected to the bias of the N first transistors. The DAC could have twelve bits with, for example, N=6 and M=6.

DAC current source bias equalization topology

A regenerative comparator with a differential amplifier pair of transistors (Q.sub.1D, Q.sub.1E, Q.sub.2D, and Q.sub.2E) and a differential regenerative pair of transistors (Q.sub.3D, Q.sub.3E, Q.sub.4D, and Q.sub.4E), utilizes one or more of the following three techniques to reduce hysteresis by reducing the amount of charge storage in transistors. First, the transistors are arranged in a bootstrap cascode configuration having a depletion mode device (Q.sub.D) and an enhancement mode device (Q.sub.E). Second, a differential amplifier pair source-coupling implementation (D.sub.1 -D.sub.4, Q.sub.5A -Q.sub.5C, and Q.sub.6A -Q.sub.6C) allows current to flow through the transistors of the differential amplifier pair and differential regenerative pair independent of whether current is flowing through the branch (52 or 4) that connects the emitters or sources of the enhancement devices of the amplifier pair and regenerative pair. Third, the comparator includes keep-alive current sources (Q.sub.KA1 -Q.sub.KA4) that allow current to flow through the amplifier pair and regenerative pair independent of the magnitude of the difference in gate input voltages being compared.

Low-hysteresis regenerative comparator

The source and drain of a first depletion-mode MESFET (DFET) define the controlled current path of a switch, the switch being open or closed depending on whether the gate-to-source voltage (V.sub.gs) for the first DFET is greater or less than the pinch-off voltage (V.sub.p) for the first DFET. The first DFET has its gate connected to a first circuit node. A second DFET, connected as a source follower, has its gate connected to the source of the first DFET. A first diode has its anode connected to the first circuit node and its cathode connected to a second circuit node. A second diode has its cathode connected to the second circuit node and its a node connected to the source of the second DFET. At least one additional diode is connected anti-parallel to the first diode between the first and second nodes. A constant current source draws current either through the first diode or through the additional diode(s) in dependence upon the state of a control signal applied to a current steering network connected across the first diode.

Growing community of inventors

Newberg, OR, United States of America

Frederick George Weiss