International Business Machines Corporation

Frederick E Strietelmeier

James O Nicholson

Chester A Heath

John Thomas O'Quin, Ii

John C O'Quin, Iii

James D Reid

A computer system having a plurality of devices which transmit and receive information over a channel is presented. The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access. Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit. At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal. All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel. Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique. Thus, each device is dynamically programmable to operate in a linear mode or a fairness mode depending on user and/or application needs. Additionally, each local arbiter includes a circuit which detects whether the device is a burst transfer device or a single transfer device.

Computer system having dynamically programmable linear/fairness priority

A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.

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Austin, TX, United States of America

Frederick E Strietelmeier