Honeywell Information Systems Inc.

Frederick E Kobs

Joseph L Ryan

Richard R Watkins

Elias Safdie

Minoru Inoshita

John P Stafford

Gerald N Winfrey

Richard A Slater

A logical control system is provided for accommodating both single and double byte accesses to a video terminal system display memory to supply video character and visual attribute data to a video screen without limiting the quantity of visual attributes and without the needless occupation of video screen character positions by visual attribute characters.

Access control logic for video terminal display memory

A logic memory control system for accommodating plural read/write requests to a video terminal display memory is provided without the need for multiplexing common busses shared by the video terminal logic devices accessing the display memory, or for compromising video terminal data transfer rates.

CRT Refresh memory system

Apparatus in a Cathode Ray Tube (CRT) display allows the sharing of the system bus between the microprocessor (CPU) and Direct Memory Access (DMA) devices without degrading the CPU performance by splitting the system bus cycle into an address phase and a data phase.

Split system bus cycle for direct memory access of peripherals in a

A microprocessor controlled cathode ray tube display system has a plurality of peripheral devices all connected in common to a system bus. Apparatus in each peripheral device activates a single interrupt signal. A single acknowledge response signal to all the devices enables the interrupting device to place its address signals on the system bus thereby initiating a firmware routine for making the interrupting device operative with the system.

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Pepperell, MA, United States of America

Frederick E Kobs