Analog Devices Technology

Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Analog Devices Global

Analog Devices Global Unlimited Company

Frederick Carnegie Thompson

John Jude O'Donnell

John Cullinane

Barry L Stakely

Jose Barreiro Silva

Declan M Dalton

Riccardo Tonietto

Varun Agrawal

Patrick Alan O'Connell

Niall McDermott

Patrick Alan O'CONNELL

Niall Mcdermott

An 'all-digital' operational amplifier architecture, that does not have the constraint of maintaining devices in their saturation region, can leverage the high speed achievable by deeply scaled technology to replace traditional linear current referenced continuous-time operational amplifier circuits with CMOS-like dynamic circuits that require no referencing structure, have no static power consumption, and are compatible with ultra-low supply voltages. Techniques are described to replace analog continuous-time linear operational amplifier input and output stages by a discrete-time comparator circuit, e.g., CMOS-style, and a switched capacitor charge pump circuit, respectively.

Analog-to-digital converter using discrete time comparator and switched capacitor charge pump

This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.

Jitter reduction techniques when using digital PLLs with ADCs and DACs

A method for controlling a gain applied to an audio signal. The method comprises applying a gain step to a gain setting at defined time intervals, and upon detection of at least one zero crossing point within the audio signal, applying the gain setting to a gain control signal for controlling the gain applied to the audio signal.

Electronic device and integrated circuit comprising a gain control module and method therefor

A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.

Flash ADC shuffling

A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Bit error rate timer for a dynamic latch

Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.

Use of a DLL to optimize an ADC performance

Tri-level scrambling in a digital to analog converter system is achieved by, in response to a tri-level binary code input, disabling a negative data directed scrambler circuit when the input code is in the positive cycle portion, disabling a positive data directed scrambler circuit when the input code is in the negative cycle portion and disabling both scrambler circuits upon a zero input code for reducing low level distortion due to a reversal of current during crossover between those cycles.

Digital to analog converter system and method with multi-level scrambling

A digital to analog converter (DAC) module receives an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency. The DAC module includes an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal.

Growing community of inventors

Foynes, Ireland

Frederick Carnegie Thompson